 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation (http://www.renesas.com) send any inquiries to http://www.renesas.com/inquiry.
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas el ectronics products li sted herein, please confirm the latest product information with a renesas electronics sales office. also , please pay regular and careful attention to additional and different information to be disclosed by rene sas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringeme nt of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electroni cs products or techni cal information descri bed in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyri ghts or other intell ectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any re nesas electronics product, wh ether in whole or in part . 4. descriptions of circuits, software and other related informat ion in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully re sponsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this doc ument, you should comply with the applicable export control laws and regulations and follow the proc edures required by such laws and re gulations. you should not use renesas electronics products or the technology described in this docum ent for any purpose relating to mil itary applicati ons or use by the military, including but not l imited to the development of weapons of mass de struction. renesas electronics products and technology may not be used for or incor porated into any products or systems whose manufacture, us e, or sale is prohibited under any applicable dom estic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing th e information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products ar e classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product de pends on the product?s quality grade, as indicated below. you must check the qua lity grade of each renesas electronics pr oduct before using it in a particular application. you may not use any renesas electronics produc t for any application categorized as ?speci fic? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. re nesas electronics shall not be in any way liable for any damages or losses incurred by you or third partie s arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intende d where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electr onics data sheets or data books, etc. ?standard?: computers; office equipmen t; communications e quipment; test and measurement equipment; audio and visual equipment; home electronic a ppliances; machine tools; personal electronic equipmen t; and industrial robots. ?high quality?: transportation equi pment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specif ically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support device s or systems), surgical im plantations, or healthcare intervention (e.g. excision, etc.), and any other applicati ons or purposes that pose a di rect threat to human life. 8. you should use the renesas electronics pr oducts described in this document within the range specified by renesas electronics , especially with respect to the maximum ra ting, operating supply voltage range, movement power volta ge range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its produc ts, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate a nd malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physic al injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safe ty design for hardware and software in cluding but not limited to redundancy, fire control and malfunction prevention, appropri ate treatment for aging degradation or an y other appropriate measures. because the evaluation of microcomputer software alone is very difficult , please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesa s electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regul ate the inclusion or use of c ontrolled substances, including wi thout limitation, the eu rohs directive. renesas electronics assumes no liability for damage s or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in w hole or in part, without prio r written consent of renes as electronics. 12. please contact a renesa s electronics sales office if you have any questi ons regarding the informat ion contained in this document or renesas electroni cs products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics. user?s manual pd78f9232 pd78f9234 pd78f9232(a) pd78f9234(a) pd78f9232(a2) pd78f9234(a2) 78k0s/kb1+ 8-bit single-chip microcontrollers 2005 printed in japan document no. u17446ej5v0ud00 (5th edition) date published november 2009 ns user?s manual u17446ej5v0ud 2 [memo] user?s manual u17446ej5v0ud 3 notes for cmos devices (1) voltage application waveform at input pin: wa veform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cm os device stays in the ar ea between vil (max) and vih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the i nput level passes through the area between vil (max) and vih (min). (2) handling of unused input pins: unconnected cm os device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input le vel may be generated due to noise, etc., causing malfunction. cmos devices behave differently t han bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) precaution against esd: a strong electric fiel d, when exposed to a mos dev ice, can cause destruction of the gate oxide and ultimately degr ade the device operation. steps mu st be taken to stop generation of static electricity as much as possible, and quickly dissi pate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electric ity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operat or should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. (4) status before initialization: power-on does not nece ssarily define the initial st atus of a mos device. immediately after the power source is turned on, devic es with reset functions have not yet been initialized. hence, power-on does not guar antee output pin levels, i/o settings or cont ents of registers. a device is not initialized until the reset signal is received. a rese t operation must be executed immediately after power-on for devices with reset functions. (5) power on/off sequence: in the case of a device t hat uses different power supplies for the internal operation and external interface, as a rule, switch on t he external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal element s of the device, causing malfuncti on and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related spec ifications governing the device. (6) input of signal during power off state : do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abno rmal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power o ff state must be judged separately for each device and according to related s pecifications gover ning the device. user?s manual u17446ej5v0ud 4 windows is a registered trademark or a trademark of microso ft corporation in the united states and/or other countries. pc/at is a trademark of internati onal business machines corporation. hp9000 series 700 and hp-ux are trad emarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademar ks of sun microsystems, inc. superflash is a registered trademark of silicon st orage technology, inc. in several countries including the united states and japan. caution: this product uses superflash ? technology licensed from silicon storage technology, inc. ? the information in this document is curr ent as of november, 2009. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec el ectronics data sheets or data books, etc., for the most up-to-date specifications of nec el ectronics products. not all products and/or types are av ailable in every country. please check with a n nec electronics sales representative for av ailability and additional information. ? no part of this document may be copied or reproduced in any form or by any means without the pr ior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. ? nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights o f third parties by or arising from the use of nec electronics pr oducts listed in this document or any other liability arising fro m the use of such products. no licens e, express, implied or otherwise, is granted under any patents, copyrights or other intellectua l property rights of nec electronics or others. ? descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and app lication examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third par ties arising from the use of these circuits, software and information. ? while nec electronics endeavors to enhance the quality, reliab ility and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to mini mize risks of damage to property or injury (including death) to persons arising from def ects in nec electronics products, cust omers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. ? nec electronics products are cl assified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a cu stomer-designated "quality assurance program" for a specific app lication. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. custom ers must check the quality grade of each ne c electronics product before using it in a particular application. "standard": computers, office equipm ent, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, ma chine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control system s, anti-disaster systems, anti- crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipmen t, submersible repeaters, nuclear reacto r control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expre ssly specified in nec electronics data sheets or data books, etc. if customers wish to use nec elec tronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note 1) "nec electronics" as used in th is statement means nec electronics corpor ation and also includes its majority-owned subsidiaries. (note 2) "nec electronics products" m eans any product developed or manufactured by or for nec electronics (as defined above). (m8e0909) user?s manual u17446ej5v0ud 5 introduction target readers this manual is intended for user engineer s who wish to understand the functions of the 78k0s/kb1+ in order to desi gn and develop its application systems and programs. the target devices are t he following subseries products. ? 78k0s/kb1+: pd78f9232, 78f9234, 78f9232(a) , 78f9234(a), 78f9232(a2), 78f9234(a2) purpose this manual is intended to give users on understanding of the f unctions described in the organization below. organization two manuals are available for the 78k0s /kb1+: this manual and the instruction manual (common to the 78k/0s series). 78k0s/kb1+ user?s manual 78k/0s series instructions user?s manual ? pin functions ? internal block functions ? interrupts ? other internal peripheral functions ? electrical specifications ? cpu function ? instruction set ? instruction description how to use this manual it is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. ? to understand the overall functions of 78k0s/kb1+ read this manual in the order of the contents . the mark user?s manual u17446ej5v0ud 6 conventions data significance: higher digits on the left and lower digits on the right active low representation: (overscore over pin or signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representation: binary ... or b decimal ... hexadecimal ... h related documents the related documents indicated in this pub lication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. 78k0s/kb1+ user?s manual this manual 78k/0s series instructions user?s manual u11047e documents related to developmen t software tools (user?s manuals) document name document no. operation u17391e language u17390e ra78k0s ver.2.00 assembler package structured assembly language u17389e operation u17416e cc78k0s ver.2.00 c compiler language u17415e operation u18601e sm+ system simulator user open interface u18212e id78k0s-qb ver.3.00 integrated debugger operation u18493e pm+ ver.6.30 u18416e documents related to development hardware tools (user?s manuals) document name document no. qb-78k0skx1 in-circuit emulator u18219e qb-mini2 on-chip debug emulator with programming function u18371e documents related to flash me mory writing (u ser?s manuals) document name document no. pg-fp5 flash memory programmer u18865e qb-programmer programming gui operation u18527e caution the related docum ents listed above are subject to change without notice. be sure to use the latest version of each document for designing. user?s manual u17446ej5v0ud 7 other related documents document name document no. semiconductor selection guide - products and packages - x13769x semiconductor device mount manual note quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devi ces by electrostatic discharge (esd) c11892e note see the ?semiconductor device mount manual? webs ite (http://www.necel.com/pkg/en/mount/index.html). caution the related docum ents listed above are subject to change without notice. be sure to use the latest version of each document for designing. user?s manual u17446ej5v0ud 8 contents chapter 1 overview.......................................................................................................... ...............14 1.1 features .................................................................................................................. .......................14 1.2 ordering information...................................................................................................... ..............15 1.3 pin configuration (top vi ew) .............................................................................................. ........16 1.4 78k0s/kx1+ product lineup ................................................................................................. .......18 1.5 block diagram............................................................................................................. ..................19 1.6 functional outline ........................................................................................................ ................20 chapter 2 pin functio ns .................................................................................................... ...........21 2.1 pin function list......................................................................................................... ..................21 2.2 pin functions ............................................................................................................. ...................23 2.2.1 p00 to p03 (por t 0)..................................................................................................... .......................23 2.2.2 p20 to p23 (por t 2)..................................................................................................... .......................23 2.2.3 p30 to p34 (por t 3)..................................................................................................... .......................23 2.2.4 p40 to p47 (por t 4)..................................................................................................... .......................24 2.2.5 p120 to p123 (por t 12).................................................................................................. ....................24 2.2.6 p130 (port 13) .......................................................................................................... .........................24 2.2.7 reset ................................................................................................................... ...........................24 2.2.8 x1 and x2............................................................................................................... ...........................25 2.2.9 av ref ............................................................................................................................... ..................25 2.2.10 av ss ............................................................................................................................... .................25 2.2.11 v dd ............................................................................................................................... ...................25 2.2.12 v ss ............................................................................................................................... ....................25 2.3 pin i/o circuits and connection of unused pins ... ...................................................................26 chapter 3 cpu archi tecture ................................................................................................. .....28 3.1 memory space .............................................................................................................. ................28 3.1.1 internal progr am memory space........................................................................................... .............30 3.1.2 internal dat a memory space .............................................................................................. ................30 3.1.3 special function register (s fr) area.................................................................................... ..............31 3.1.4 data me mory addr essing .................................................................................................. ................31 3.2 processor registers....................................................................................................... ..............33 3.2.1 contro l regist ers ....................................................................................................... .........................33 3.2.2 general-pur pose regi sters............................................................................................... ..................36 3.2.3 special functi on register s (sfrs) ....................................................................................... ...............37 3.3 instruction address addressi ng............................................................................................ .....42 3.3.1 relati ve addre ssing ..................................................................................................... ......................42 3.3.2 immedi ate addre ssing .................................................................................................... ...................43 3.3.3 table indi rect addr essing ............................................................................................... ...................43 3.3.4 regist er addre ssing ..................................................................................................... ......................44 3.4 operand address addressing................................................................................................ .....45 3.4.1 direc t addre ssing ....................................................................................................... .......................45 3.4.2 short di rect addr essing................................................................................................. .....................46 3.4.3 special function r egister (sfr ) addre ssing .............................................................................. .........47 3.4.4 regist er addre ssing ..................................................................................................... ......................48 user?s manual u17446ej5v0ud 9 3.4.5 register i ndirect addr essing............................................................................................ .................. 49 3.4.6 bas ed addre ssing ........................................................................................................ ..................... 50 3.4.7 sta ck addre ssing ........................................................................................................ ....................... 51 chapter 4 port f unctions................................................................................................... ........ 52 4.1 functions of ports........................................................................................................ ................ 52 4.2 port configuration........................................................................................................ ................ 54 4.2.1 port 0 ......................................................................................................................... ....................... 55 4.2.2 po rt 2 .................................................................................................................. .............................. 56 4.2.3 po rt 3 .................................................................................................................. .............................. 57 4.2.4 po rt 4 .................................................................................................................. .............................. 60 4.2.5 po rt 12 ................................................................................................................. ............................. 63 4.2.6 po rt 13 ................................................................................................................. ............................. 65 4.3 registers controlling port func tions ...................................................................................... .. 66 4.4 operation of port function ........................................... .......................................................... .... 71 4.4.1 writi ng to i/o port ..................................................................................................... ......................... 71 4.4.2 reading from i/o port................................................................................................... ..................... 71 4.4.3 operati ons on i/o port.................................................................................................. ..................... 71 chapter 5 clock generators................................... ............................................................. ... 72 5.1 functions of clock generators........................................ .......................................................... .72 5.1.1 system cl ock osc illators ................................................................................................ .................... 72 5.1.2 clock oscillator for interval time generat ion........................................................................... ............ 72 5.2 configuration of clock generators ............................ ............................................................. ... 73 5.3 registers controlling clock generators.................... ................................................................ 75 5.4 system clock oscillators .................................................................................................. .......... 78 5.4.1 high-speed inte rnal osc illator .......................................................................................... .................. 78 5.4.2 crystal/cer amic osc illator .............................................................................................. .................... 78 5.4.3 external cl ock input circuit............................................................................................ ..................... 80 5.4.4 pr escale r............................................................................................................... ............................ 80 5.5 operation of cpu clock generator ............................ .............................................................. .. 81 5.6 operation of clock generator supplying clock to peripheral hardware............................... 86 chapter 6 16-bit timer/event coun ter 00............................................................................. 88 6.1 functions of 16-bit timer/event c ounter 00.............................................................................. 88 6.2 configuration of 16-bit timer/even t counter 00 ....................................................................... 89 6.3 registers to control 16-bit timer/event counter 00 ................................................................ 93 6.4 operation of 16-bit timer/event c ounter 00.............................................................................. 99 6.4.1 interval timer oper ation ................................................................................................ ..................... 99 6.4.2 external event counter operatio n ........................................................................................ ............ 101 6.4.3 pulse width m easurement operati ons ...................................................................................... ....... 104 6.4.4 square-wave output oper ation ............................................................................................ ............ 112 6.4.5 ppg out put operat ions................................................................................................... ................. 114 6.4.6 one-shot pul se output operatio n ......................................................................................... ............ 117 6.5 cautions related to 16-bit timer/event counter 00 ............................................................... 122 chapter 7 8-bit timer 80.................................................................................................. ............ 129 7.1 function of 8-bit ti mer 80 ................................................................................................ ......... 129 user?s manual u17446ej5v0ud 10 7.2 configuration of 8-bit ti mer 80 ........................................................................................... ......130 7.3 register controlling 8-bit timer 80.................. ..................................................................... ....132 7.4 operation of 8-bit timer 80 ............................................................................................... .........133 7.4.1 operation as interval timer ............................................................................................. .................133 7.5 notes on 8-bit timer 80 ................................................................................................... ...........135 chapter 8 8-bit time r h1 .................................................................................................. ...........136 8.1 functions of 8-bit timer h1 .................................................................................................... ...136 8.2 configuration of 8-bit ti mer h1........................................................................................... ......136 8.3 registers controlling 8-bit timer h1 ....................... ............................................................... ..139 8.4 operation of 8-bit timer h1 ............................................................................................... ........142 8.4.1 operation as interv al timer/squar e-wave output .......................................................................... ....142 8.4.2 operation as pwm output mode ............................................................................................ .........145 chapter 9 watchdog timer ................................................................................................... ....151 9.1 functions of watchdog timer ............................................................................................... ....151 9.2 configuration of watchdog time r ........................................................................................... .153 9.3 registers controlling watchdog timer............................ ........................................................15 4 9.4 operation of watchdog time r ............................................................................................... ....156 9.4.1 watchdog timer operation when ?low-speed inter nal oscillator cannot be stopped? is selected by option byte.................................................................................................................... ...................156 9.4.2 watchdog timer operation when ?low-speed inte rnal oscillator can be stopped by software? is selected by option byte........................................................................................................ ............158 9.4.3 watchdog timer operation in stop mode (w hen ?low-speed internal oscillator can be stopped by software? is select ed by opti on byte ) .......................................................................................... .....160 9.4.4 watchdog timer operation in halt mode (w hen ?low-speed internal oscillator can be stopped by software? is select ed by opti on byte ) .......................................................................................... .....162 chapter 10 a/d converter ................................................................................................... ......163 10.1 functions of a/d conver ter..................................................................................................... 163 10.2 configuration of a/d converter ............................. .............................................................. ...165 10.3 registers used by a/d converter...........................................................................................167 10.4 a/d converter operations ....................................................................................................... 172 10.4.1 basic operations of a/d c onverter ...................................................................................... ...........172 10.4.2 input voltage and conversion results ................................................................................... ..........174 10.4.3 a/d conver ter operati on m ode........................................................................................... ............175 10.5 how to read a/d converter characteristics table..... ..........................................................177 10.6 cautions for a/d converter ..................................................................................................... 179 chapter 11 serial interface uart6 ............................ ..........................................................182 11.1 functions of serial interface uart6 ................................. .....................................................182 11.2 configuration of serial interface uart6................................................................................186 11.3 registers controlling serial interf ace uart6.......................................................................189 11.4 operation of serial interface uart6 .............................. ........................................................198 11.4.1 operat ion stop mode .................................................................................................... .................198 11.4.2 asynchronous serial interface (u art) mode .............................................................................. ..199 11.4.3 dedicated baud rate generat or .......................................................................................... ............213 user?s manual u17446ej5v0ud 11 chapter 12 multiplier ....................................................................................................... ........... 220 12.1 multiplier function ............................................................................................................ ....... 220 12.2 multiplier configuration ....................................................................................................... .... 220 12.3 multiplier control register .......................................... .......................................................... .. 222 12.4 multiplier operatio n ........................................................................................................... ...... 223 chapter 13 interrupt functions ................................... ......................................................... 2 25 13.1 interrupt function types................................................. ...................................................... .. 225 13.2 interrupt sources and configuration . .................................................................................... 226 13.3 interrupt function control registers . .................................................................................... 228 13.4 interrupt servicing operation ....... .......................................................................................... 2 33 13.4.1 maskable interrupt reques t acknowledgment operatio n ................................................................ 233 13.4.2 multiple in terrupt se rvicing........................................................................................... .................. 235 13.4.3 interrupt request pending .............................................................................................. ................ 237 chapter 14 standby function...................................... .......................................................... .. 238 14.1 standby function and configuration.. ................................................................................... 238 14.1.1 standby func tion ....................................................................................................... .................... 238 14.1.2 registers used duri ng st andby .......................................................................................... ............ 240 14.2 standby function operation........................................... ........................................................ 24 1 14.2.1 ha lt m ode .............................................................................................................. ..................... 241 14.2.2 st op m ode .............................................................................................................. .................... 244 chapter 15 reset function .................................................................................................. ..... 248 15.1 register for confirming reset sour ce................................................................................... 255 chapter 16 power-on-clear circui t ..................................................................................... 256 16.1 functions of power-on-clear circuit . .................................................................................... 256 16.2 configuration of power-on-clear circ uit ............................................................................... 257 16.3 operation of power-on-clear circuit ...................................................................................... 257 16.4 cautions for power-on-clear circuit ...................................................................................... 258 chapter 17 low-voltage detector........................... ............................................................ 260 17.1 functions of low-voltage detect or........................................................................................ 260 17.2 configuration of low-voltage de tector ................................................................................. 260 17.3 registers controlling low-voltage detector........... .............................................................. 261 17.4 operation of low-voltage det ector........................................................................................ 263 17.5 cautions for low-voltage detector .......................... .............................................................. 266 chapter 18 option byte ...................................................................................................... ......... 269 18.1 functions of option byte ......................................... ........................................................ ....... 269 18.2 format of option byte .................................................................................................... ......... 270 18.3 caution when the reset pin is used as an i nput-only port pin (p34) ............................. 271 chapter 19 flash memory.................................................................................................... ...... 272 19.1 features................................................................................................................. .................... 272 19.2 memory configuration ............................................... ...................................................... ........ 273 user?s manual u17446ej5v0ud 12 19.3 functional outline ....................................................................................................... .............273 19.4 writing with flash memory programmer ..................... ..........................................................274 19.5 programming environment .................................................................................................. ...275 19.6 pin connection on board.................................................................................................. .......277 19.6.1 x1 and x2 pins ......................................................................................................... .....................277 19.6.2 r eset pin.............................................................................................................. .......................278 19.6.3 po rt pi ns .............................................................................................................. ..........................279 19.6.4 powe r suppl y........................................................................................................... ......................279 19.7 on-board and off-board flash memory programmi ng ........................................................280 19.7.1 flash memory programmi ng m ode.......................................................................................... ......280 19.7.2 communi cation co mmands ................................................................................................. ..........280 19.7.3 securi ty se ttings ...................................................................................................... ......................281 19.8 flash memory programming by self programming.... ..........................................................282 19.8.1 outline of self progr amming ............................................................................................ ..............282 19.8.2 cautions on self programming functi on .................................................................................. .......285 19.8.3 registers used for self programmi ng func tion ........................................................................... ....285 19.8.4 example of shifting normal mode to self pr ogramming mode ........................................................293 19.8.5 example of shifting self programming mode to normal mode ........................................................296 19.8.6 example of block erase oper ation in self pr ogramming mode .......................................................299 19.8.7 example of block blank check operation in self programming mode .............................................302 19.8.8 example of byte write oper ation in self pr ogramming mode ..........................................................305 19.8.9 examples of internal verify operation in self programming mode ..................................................308 19.8.10 examples of operation w hen command execution time should be minimized in self programming mode ........................................................................................................................... ................312 19.8.11 examples of operation w hen interrupt-disabled time should be minimized in self programming mode ........................................................................................................................... ................319 chapter 20 on-chip debug function ............................... ........................................................330 20.1 connecting qb-mini2 to 78k0s/kb1+.......................... ..........................................................330 20.1.1 connection of intp 3 pin ................................................................................................ ...............331 20.1.2 connection of x1 and x2 pins ........................................................................................... ............332 20.2 securing of user resources ............................................................................................... ......333 chapter 21 instruction set overview ....................... ..........................................................334 21.1 operation ................................................................................................................ ...................334 21.1.1 operand identifiers and descripti on met hods ............................................................................ ....334 21.1.2 description of ?operation? column ...................................................................................... ...........335 21.1.3 description of ?flag? column........................................................................................... ...............335 21.2 operation list ........................................................................................................... ................336 21.3 instructions listed by a ddressing type ................................................................................341 chapter 22 electrical specifications (standard pr oduct, (a) grade product) ................344 chapter 23 electrical specifications ((a2) grade pr oduct) ..... .........................................356 chapter 24 package drawing ................................................................................................. .370 chapter 25 recommended soldering conditions... ........................................................373 user?s manual u17446ej5v0ud 13 appendix a development tools .............................................................................................. 3 75 a.1 software package .......................................................................................................... ............ 378 a.2 language processing software ................................... ........................................................... .378 a.3 flash memory writing tools................................................................................................ ..... 379 a.3.1 when using flash memory programmer pg-fp5 and fl-p r5........................................................ 379 a.3.2 when using on-chip debug emulator with progra mming function qb-mini2................................... 379 a.4 debugging tools (hardware)........................................ ........................................................ .... 379 a.4.1 when using in-circu it emulator qb-78k 0skx1.............................................................................. . 379 a.4.2 when using on-chip debug emulator with progra mming function qb-mini2................................... 380 a.5 debugging tools (software)....................................... ......................................................... ..... 381 appendix b notes on designing target system ................................................................ 382 appendix c register index .................................................................................................. ....... 384 c.1 register index (register name) ................................... ............................................................ 38 4 c.2 register index (symbol)................................................................................................... ......... 387 appendix d list of cautions............................................................................................... ...... 390 appendix e revision history ................................................................................................ ..... 410 e.1 major revisions in this edition........................................................................................... ..... 410 e.2 revision history up to previous editions ................ ............................................................... 411 user?s manual u17446ej5v0ud 14 chapter 1 overview 1.1 features o 78k0s cpu core o rom and ram capacities item part number program memory (flash memory) memory (internal high-speed ram) pd78f9232 4 kb pd78f9234 8 kb 256 bytes o minimum instruction execution time: 0.2 s (with 10 mhz@4.0 to 5.5 v operation) o clock ? high-speed system clock ? selected from the following three sources - ceramic/crystal resonator: 2 to 10 mhz (standard product, (a) grade product) 2 to 8 mhz ((a2) grade product) - external clock: 2 to 10 mhz (standard product, (a) grade product) 2 to 8 mhz ((a2) grade product) - high-speed internal oscillator: 8 mhz 3% ( ? 10 to +80 c), 8 mhz 5% (standard product, (a) grade product: ? 40 to +85 c, (a2) grade product: ? 40 to +125 c) ? low-speed internal oscillator 240 khz (typ.) ? watc hdog timer, timer clock in intermittent operation o i/o ports: 26 (cmos i/o: 24, cmos input: 1, cmos output: 1) o timer: 4 channels ? 16-bit timer/event counter: 1 channel ? timer output 1, capture input 2 ? 8-bit timer: 2 channels ? pwm output 1 ? watchdog timer: 1 channel ? operable with low-speed internal oscillation clock o serial interface: uart (lin (local interconnect network) bus supported) 1 channel o on-chip multiplier: 8 bits 8 bits = 16 bits o 10-bit resolution a/d converter: 4 channels o on-chip power-on-clear (poc) circuit (a reset is aut omatically generated when the vo ltage drops to 2.1 v (typ.) or below.) o on-chip low voltage detector (lvi) circuit (an interrup t/reset (selectable) is gener ated when the detection voltage is reached.) ? detection voltage: selectable from ten levels between 2.35 and 4.3 v o single-power-supply flash memory ? flash self programming enabled ? software protection function: protected from outside party c opying (no flash reading command) ? time required for writing by dedicated flash memo ry programmer: approximately 3 seconds (4 kb) ? flash programming on mass production lines supported o safety function ? watchdog timer operated by clock independent from cpu ? a hang-up can be detected even if the system clock stops ? supply voltage drop detectable by lvi ? appropriate processing can be executed bef ore the supply voltage drops below the operation voltage ? equipped with option byte function ? important system operation settings set in hardware chapter 1 overview user?s manual u17446ej5v0ud 15 o assembler and c language supported o enhanced development environment ? support for full-function emulator (iecube), simplified emulator (minicube2), and simulator o supply voltage: v dd = 2.0 to 5.5 v ? use these products in the following voltage range because t he detection voltage (v poc ) of the poc circuit is the supply voltage range. standard product, (a) grade product: 2.2 to 5. 5 v, (a2) grade product: 2.26 to 5.5 v o operating temperature range ? standard product, (a) grade product: t a = ? 40 to +85 c ? (a2) grade product: t a = ? 40 to +125 c 1.2 ordering information part number pd78f9 - ( ) - - semiconductor component -a product contains no lead in any area (terminal finish is sn/bi plating) -ax lead-free product contains no lead in any area (terminal finish is ni/pd/au plating) quality grades blank standard (for ordinary electronic systems) (a) (a2) special (for high-reli ability electronic systems) package type mc-5a4 mc-cab 30-pin plastic ssop cs-caa 32-pin plastic sdip high-speed ram flash memory 232 256 bytes 4 k bytes 234 256 bytes 8 k bytes product type f flash memory versions please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec electronics corporation to know the specification of the quality grade on the device and its recommended applications. [part number list] pd78f9232mc-5a4-a pd78f9234mc-5a4-a pd78f9232mc(a)-5a4-a pd78f9234mc(a)-5a4-a pd78f9232mc(a2)-5a4-a pd78f9234mc(a2)-5a4-a pd78f9232mc(a)-cab-ax pd78f9234mc(a)-cab-ax pd78f9232mc(a2)-cab-ax pd78f9234mc(a2)-cab-ax pd78f9232cs-caa-a pd78f9234cs-caa-a chapter 1 overview user?s manual u17446ej5v0ud 16 1.3 pin configuration (top view) ? 30-pin plastic ssop p03 p02 p01 p00 p123 v ss v dd p121/x1 p122/x2 p33 p34/reset p32 p31/ti010/to00/intp2 p30/ti000/intp0 p40 28 27 26 30 29 25 24 23 22 21 20 19 18 16 p120 av ss av ref p20/ani0 p21/ani1 p22/ani2 p23/ani3 p130 p47 p45 p46 p44/rxd6 p43/txd6/intp1 p42/toh1 p41/intp3 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14 15 caution connect the av ss pin to v ss . ? 32-pin plastic sdip p23/ani3 p22/ani2 p21/ani1 p20/ani0 av ref av ss av ss p120 p03 p01 p02 p00 p123 v ss v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 v dd 16 30 29 28 32 31 27 26 25 24 23 22 21 20 18 p130 p47 p46 p45 p44/rxd6 p43/txd6/intp1 p42/toh1 p41/intp3 p40 p31/ti010/to00/intp2 p30/ti00/intp0 p32 p33 p34/reset p122/x2 19 17 p121/x1 caution connect the av ss pin to v ss . chapter 1 overview user?s manual u17446ej5v0ud 17 pin name ani0 to ani3: analog input p130: port 13 av ref : analog power supply, reset: reset analog reference voltage, rxd6: receive data power supply for p20 to p23 ti000, ti010: timer input av ss : analog ground to00, toh1: timer output intp0 to intp3: external interrupt input txd6: transmit data p00 to p03: port 0 v dd : power supply p20 to p23: port 2 v ss : ground p30 to p34: port 3 x1, x2: crystal oscillator (x1 input clock) p40 to p47: port 4 p120 to p123: port 12 chapter 1 overview user?s manual u17446ej5v0ud 18 1.4 78k0s/kx1+ product lineup the following table shows the pr oduct lineup of the 78k0s/kx1+. part number item 78k0s/ku1+ 78k0s/ky1+ 78k0s/ka1+ 78k0s/kb1+ number of pins 10 pins 16 pins 20 pins 30/32 pins flash memory 1 kb, 2 kb, 4 kb 2 kb 4 kb, 8 kb 4 kb, 8 kb internal memory ram 128 bytes 128 bytes 256 bytes 256 bytes supply voltage v dd = 2.0 to 5.5 v note 1 minimum instruction execution time 0.20 s (10 mhz, v dd = 4.0 to 5.5 v) 0.33 s (6 mhz, v dd = 3.0 to 5.5 v) 0.40 s (5 mhz, v dd = 2.7 to 5.5 v) 1.0 s (2 mhz, v dd = 2.0 to 5.5 v) system clock (oscillation frequency) high-speed internal oscillation (8 mhz (typ.)) crystal/ceramic oscillation (2 to 10 mhz) note 2 external clock input oscillation (2 to 10 mhz) clock for tmh1 and wdt (oscillation frequency) low-speed internal oscillation (240 khz (typ.)) cmos i/o 7 13 15 24 cmos input 1 1 1 1 port cmos output ? ? 1 1 16-bit (tm0) 1 ch note 3 8-bit (tmh) 1 ch 8-bit (tm8) ? 1 ch timer wdt 1 ch serial interface ? lin-bus-supporting uart: 1 ch a/d converter note 4 10 bits: 4 ch (2.7 to 5.5 v) note 4 multiplier (8 bits 8 bits) ? provided internal 5 note 5 9 interrupts external 2 4 reset pin provided poc 2.1 v (typ.) lvi provided (select able by software) reset wdt provided operating temperature range standard product: ? 40 to +85 c standard product, (a) grade product: ? 40 to +85 c (a2) grade product: ? 40 to +125 c notes 1. use these products in the following vo ltage range because the detection voltage (v poc ) of the power-on- clear (poc) circuit is the supply voltage range. standard product, (a) grade product: 2.2 to 5. 5 v, (a2) grade product: 2.26 to 5.5 v 2. pd78f950x does not support the crystal/ceramic oscillation. 3. the product without a/d converter ( pd78f950x) in the 78k0s/k u1+ is not supported. 4. the product without a/d converter ( pd78f95xx) is provided for the 78k0s/ku1+ and 78k0s/ky1+ respectively. this product has a/d converter. 5. there are 2 and 4 factors for the products without a/d converter in the 78k0s/ku1+ and 78k0s/ky1+, respectively. chapter 1 overview user?s manual u17446ej5v0ud 19 1.5 block diagram 78k0s cpu core internal high-speed ram flash memory toh1/p42 port 2 p20 to p23 4 port 0 p00 to p03 4 port 4 p40 to p47 8 port 13 p130 power-on-clear/ low-voltage indicator poc/lvi control reset control port 3 p30 to p33 4 p34 p120 to p123 4 port 12 system control high-speed internal oscillator reset/p34 x1/p121 x2/p122 low-speed internal oscillator intp0/p30 intp1/p43 intp2/p31 intp3/p41 ani0/p20 to ani3/p23 4 a/d converter av ref av ss 8-bit timer 80 watchdog timer multiplier 8-bit timer h1 16-bit timer/ event counter 00 to00/ti010/p31 ti000/p30 rxd6/p44 txd6/p43 serial interface uart6 interrupt control v ss v dd chapter 1 overview user?s manual u17446ej5v0ud 20 1.6 functional outline item pd78f9232 pd78f9234 flash memory 4 kb 8 kb internal memory high-speed ram 256 bytes memory space 64 kb x1 input clock (oscillation frequency) crystal/ceramic/external clock input: 10 mhz (v dd = 2.0 to 5.5 v) high speed (oscillation frequency) internal oscillation: 8 mhz (typ.) internal oscillation clock low speed (for tmh1 and wdt) internal oscillation: 240 khz (typ.) general-purpose registers 8 bits 8 registers instruction execution time 0.2 s/0.4 s/0.8 s/1.6 s/3.2 s (x1 input clock: f x = 10 mhz) multiplier 8 bits 8 bits = 16 bits i/o port total: 26 pins cmos i/o: 24 pins cmos input: 1 pin cmos output: 1 pin timer ? 16-bit timer/event counter: 1 channel ? 8-bit timer (timer h1): 1 channel ? 8-bit timer (timer 80): 1 channel ? watchdog timer: 1 channel timer output 2 pins (pwm: 1 pin) a/d converter 10-bit resolution 4 channels serial interface lin-bus-s upporting uart mode: 1 channel external 4 vectored interrupt sources internal 9 reset ? reset by reset pin ? internal reset by watchdog timer ? internal reset by power-on-clear ? internal reset by low-voltage detector supply voltage v dd = 2.0 to 5.5 v note operating temperature range standard product, (a) grade product: ? 40 to +85 c (a2) grade product: ? 40 to +125 c package ? 30-pin plastic ssop ? 32-pin plastic sdip note use these products in the following voltage range because t he detection voltage (v poc ) of the power-on- clear (poc) circuit is the supply voltage range. standard product, (a) grade product: 2.2 to 5. 5 v, (a2) grade product: 2.26 to 5.5 v user?s manual u17446ej5v0ud 21 chapter 2 pin functions 2.1 pin function list (1) port pins pin name i/o function after reset alternate- function pin p00 to p03 i/o port 0. 4-bit i/o port. can be set to input or output mode in 1-bit units. an on-chip pull-up resistor can be connected by setting software. input ? p20 to p23 i/o port 2. 4-bit i/o port. can be set to input or output mode in 1-bit units. an on-chip pull-up resistor can be connected by setting software. input ani0 to ani3 p30 ti000/intp0 p31 ti010/to00/ intp2 p32 ? p33 i/o can be set to input or output mode in 1- bit units. an on-chip pull-up resistor can be connected by setting software. input ? p34 note input port 3 input only input reset note p40 ? p41 intp3 p42 toh1 p43 txd6/intp1 p44 rxd6 p45 ? p46 ? p47 i/o port 4. 8-bit i/o port. can be set to input or output mode in 1-bit units. an on-chip pull-up resistor can be connected by setting software. input ? p120 ? p121 note x1 note p122 note x2 note p123 i/o port 12. 4-bit i/o port. can be set to input or output mode in 1-bit units. an on-chip pull-up resistor can be connected only to p120 and p123 by setting software. input ? p130 output port 13. 1-bit output-only port output ? note for settings of alternate function, refer to chapter 18 option byte . caution the p121/x1 and p122/x2 pins are pulled down during reset. chapter 2 pin functions user?s manual u17446ej5v0ud 22 (2) non-port pins pin name i/o function after reset alternate- function pin intp0 p30/ti000 intp1 p43/txd6 intp2 p31/ti010/to00 intp3 input external interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input p41 rxd6 input serial data input for asyn chronous serial interface input p44 txd6 output serial data output for asynch ronous serial interface input p43/intp1 ti000 external count clock input to 16-bit timer/event counter 00. capture trigger input to captur e registers (cr000 and cr010) of 16-bit timer/event counter 00 p30/intp0 ti010 input capture trigger input to captur e register (cr000) of 16-bit timer/event counter 00 input p31/to00/intp2 to00 output 16-bit timer/event counter 00 output input p31/ti010/intp2 toh1 output 8-bit timer h1 output input p42 ani0 to ani3 input analog input of a/d converter input p20 to p23 av ref ? a/d converter reference voltage input and positive power supply for p20 to p23 and a/d converter ? ? av ss ? a/d converter ground potential. make the same potential as v ss . ? ? reset note input system reset input ? p34 note x1 note input connection of crystal/ceramic resonator for system clock oscillation. external clock input input p121 note x2 note ? connection of crystal/ceramic resonator for system clock oscillation. input p122 note v dd ? positive power supply ? ? v ss ? ground potential ? ? note for settings of alternate function, refer to chapter 18 option byte . caution the p121/x1 and p122/x2 pins are pulled down during reset. chapter 2 pin functions user?s manual u17446ej5v0ud 23 2.2 pin functions 2.2.1 p00 to p03 (port 0) p00 to p03 function as a 4-bit i/o port. p00 to p03 can be set to input or output in 1-bit units using port mode register 0 (pm0). use of an on-chip pu ll-up resistor can be specified by pull- up resistor option register 0 (pu0). 2.2.2 p20 to p23 (port 2) p20 to p23 constitute a 4-bit i/o port, port 2. in addition to i/o port pins, these pins also have a function to input analog signals to the a/d converter. these pins can be set to the follo wing operation modes in 1-bit units. (1) port mode p20 to p23 function as a 4-bit i/o port. each bit of th is port can be set to the i nput or output mode by using port mode register 2 (pm2). in addition, an on-chip pu ll-up resistor can be connected to the port by using pull- up resistor option register 2 (pu2). (2) control mode p20 to p23 function as the analog input pins (ani0 to ani3) of the a/d conv erter. when using these pins as analog input pins, refer to 10.6 cautions for a/d conver ter (5) ani0/p20 to ani3/p23 . 2.2.3 p30 to p34 (port 3) p30 to p33 constitute a 4-bit i/o port, port 3. in addi tion to i/o port pins, p30 and p31 also have functions to input/output a timer signal, and input an external interrupt request signal. p34 is a 1-bit input-only port. this pin is also used as a reset pin, and when the power is turned on, this is the reset function. for settings of alternate function, refer to chapter 18 option byte . when using p34 as input port, pull up the p34 pin by using external resistor. p30 to p34 can be set to the following operation modes in 1-bit units. (1) port mode p30 to p33 function as a 4-bit i/o port. each bit of th is port can be set to the i nput or output mode by using port mode register 3 (pm3). in addition, an on-chip pu ll-up resistor can be connected to the port by using pull- up resistor option register 3 (pu3). p34 functions as a 1-bit input-only port. (2) control mode p30 and p31 function to input/output signals to/from inter nal timers, and to input an external interrupt request signal. (a) intp0 and intp2 these are external interrupt reques t input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) ti000 this pin inputs an external count clock to 16-bit timer/ event counter 00, or a capt ure trigger signal to the capture registers (cr000 and cr010) of 16-bit timer/event counter 00. (c) ti010 this pin inputs a capture trigger si gnal to the capture register (cr000) of 16-bit timer/event counter 00. chapter 2 pin functions user?s manual u17446ej5v0ud 24 (d) to00 this pin outputs a signal from 16-bit timer/event counter 00. 2.2.4 p40 to p47 (port 4) p40 to p47 constitute an 8-bit i/o port, port 4. in addition to i/o port pins, p41 to p44 also have functions to output a timer signal, input external interrupt request signals, and input/output the data of the serial interface. these pins can be set to the follo wing operation modes in 1-bit units. (1) port mode p40 to p47 function as an 8-bit i/o port. each bit of th is port can be set to the i nput or output mode by using port mode register 4 (pm4). in addition, an on-chip pu ll-up resistor can be connected to the port by using pull- up resistor option register 4 (pu4). (2) control mode p41 to 44 function to output a signal from an internal timer, input external interrupt request signals, and input/output data of t he serial interface. (a) intp1 and intp3 these are external interrupt reques t input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) toh1 this is the output pin of 8-bit timer h1. (c) txd6 this pin outputs serial data from t he asynchronous serial interface. (d) rxd6 this pin inputs serial data to t he asynchronous serial interface. 2.2.5 p120 to p123 (port 12) p120 to p123 constitute a 4-bit i/o port, port 12. each bit of this port can be set to the input or output m ode by using port mode register 12 (pm12). an on-chip pull- up resistor can be connected to p120 and p123 by us ing pull-up resistor option register 12 (pu12). p121 and p122 also function as the x1 and x2, respective ly. for settings of alternate function, refer to chapter 18 option byte . caution the p121/x1 and p122/x2 pins are pulled down during reset. 2.2.6 p130 (port 13) this is a 1-bit output-only port. 2.2.7 reset this pin inputs an active-low system reset signal. when t he power is turned on, this is the reset function, regardless of the option byte setting. chapter 2 pin functions user?s manual u17446ej5v0ud 25 2.2.8 x1 and x2 these pins connect an oscillator to oscillate the x1 input clock. x1 and x2 also function as the p121 and p122 pins, respec tively. for settings of alte rnate function, refer to chapter 18 option byte . supply an external clock to x1. caution the p121/x1 and p122/x2 pins are pulled down during reset. 2.2.9 av ref this is the a/d converter referenc e voltage input pin and the positive power supply pin of p20 to p23 and a/d converter. when the a/d converter is not used, connect this pin to v dd . 2.2.10 av ss this is the a/d converter ground potential pin. even when t he a/d converter is not used, always use this pin with the same potential as the v ss pin. 2.2.11 v dd this is the positive power supply pin. 2.2.12 v ss this is the ground pin. chapter 2 pin functions user?s manual u17446ej5v0ud 26 2.3 pin i/o circuits and connection of unused pins table 2-1 shows i/o circuit type of eac h pin and the connections of unused pins. for the configuration of the i/o circuit of each type, refer to figure 2-1 . table 2-1. types of pin i/o circui ts and connection of unused pins pin name i/o circuit type i/o recommended connection of unused pin p00 to p03 8-a input: independently connect to v dd or v ss via a resistor. output: leave open. p20/ani0 to p23/ani3 11 input: independently connect to av ref or v ss via a resistor. output: leave open. p30/ti000/intp0 p31/ti010/to00/intp2 p32 and p33 8-a i/o input: independently connect to v dd or v ss via a resistor. output: leave open. p34/reset 2 input connect to v dd via a resistor. p40 p41/intp3 p42/toh1 p43/txd6/intp1 p44/rxd6 p45 to p47 p120 8-a input: independently connect to v dd or v ss via a resistor. output: leave open. p121/x1 p122/x2 16-b input: independently connect to v ss via a resistor. output: leave open. p123 8-a i/o input: independently connect to v dd or v ss via a resistor. output: leave open. p130 3-c output leave open. av ref ? input connect directly to v dd . av ss ? ? connect directly to v ss . chapter 2 pin functions user?s manual u17446ej5v0ud 27 figure 2-1. pin i/o circuits in v dd p-ch n-ch data out data output disable av ref p-ch n-ch in/out av ref (threshold voltage) av ss p-ch n-ch + input enable - pull up enable v dd p-ch pull up enable data output disable v dd p-ch v dd p-ch in/out n-ch p-ch feedback cut-off x1, in/out x2, in/out osc enable data output disable v dd p-ch n-ch data output disable p-ch n-ch type 2 type 3-c type 8-a type 16-b type 11 schmitt-triggered input with hysteresis characteristics comparator v ss v ss v ss v ss v ss user?s manual u17446ej5v0ud 28 chapter 3 cpu architecture 3.1 memory space the 78k0s/kb1+ can access up to 64 kb of memory spac e. figures 3-1 and 3-2 show the memory maps. figure 3-1. memory map ( pd78f9232) special function registers (sfr) 256 8 bits internal high-speed ram 256 8 bits flash memory 4,096 8 bits use prohibited program memory space data memory space program area option byte area program area callt table area vector table area ffffh 0fffh 0080h 007fh 0082h 0081h 0040h 003fh 0022h 0021h 0000h ff00h feffh fe00h fdffh 1000h 0fffh 0000h protect byte area remark the option byte and protect byte are 1 byte each. chapter 3 cpu architecture user?s manual u17446ej5v0ud 29 figure 3-2. memory map ( pd78f9234) special function registers (sfr) 256 8 bits internal high-speed ram 256 8 bits flash memory 8,192 8 bits program memory space data memory space program area option byte area program area callt table area vector table area use prohibited ffffh 1fffh 0000h 0080h 007fh 0082h 0081h 0040h 003fh 0022h 0021h ff00h feffh fe00h fdffh 2000h 1fffh 0000h protect byte area remark the option byte and protect byte are 1 byte each. chapter 3 cpu architecture user?s manual u17446ej5v0ud 30 3.1.1 internal program memory space the internal program memory space stores programs and table data. this space is usually addressed by the program counter (pc). the 78k0s/kb1+ provides the following internal roms (or flash memory) containing the following capacities. table 3-1. internal rom capacity internal rom part number structure capacity pd78f9232 4,096 8 bits pd78f9234 flash memory 8,192 8 bits the following areas are allocated to t he internal program memory space. (1) vector table area the 34-byte area of addresses 0000h to 0021h is reserved as a vector table area. this area stores program start addresses to be used when branching by reset input or interrupt request generation. of a 16-bit address, the lower 8 bits are stored in an ev en address, and the higher 8 bits are stored in an odd address. table 3-2. vector table vector table address interrupt request vector table address interrupt request 0000h reset input 0012h intad 0006h intlvi 0016h intp2 0008h intp0 0018h intp3 000ah inp1 001ah inttm80 000ch inttmh1 001ch intsre6 000eh inttm000 001eh intsr6 0010h inttm010 0020h intst6 caution no interrupt sources corres pond to the vector table address 0014h. (2) callt instruction table area the subroutine entry address of a 1-byte call instruction (callt) can be stored in the 64-byte area of addresses 0040h to 007fh. (3) option byte area the option byte area is t he 1-byte area of address 0080h. for details, refer to chapter 18 option byte . (4) protect byte area the protect byte area is the 1-byte ar ea of address 0081h. for details, refer to chapter 19 flash memory . 3.1.2 internal data memory space pd78f9232 and pd78f9234 provide 256-byte in ternal high-speed ram. the internal high-speed ram can also be used as a stack memory. chapter 3 cpu architecture user?s manual u17446ej5v0ud 31 3.1.3 special function register (sfr) area special function registers (sfrs) of on-chip peripheral hardware are allocat ed to the area of ff00h to ffffh (see table 3-3 ). 3.1.4 data memory addressing the 78k0s/kb1+ is provided with a wide range of addressing modes to make memo ry manipulation as efficient as possible. the area (fe00h to feffh) which contains a data memory and the special function register area (sfr) can be accessed using a unique addressing mode in accordance with each function. figures 3-3 and 3-4 illustrate the data memory addressing. figure 3-3. data memory addressing ( pd78f9232) special function registers (sfr) 256 8 bits internal high-speed ram 256 8 bits flash memory 4,096 8 bits use prohibited direct addressing register indirect addressing based addressing sfr addressing short direct addressing ffffh ff00h feffh ff20h ff1fh fe20h fe1fh fe00h fdffh 1000h 0fffh 0000h chapter 3 cpu architecture user?s manual u17446ej5v0ud 32 figure 3-4. data memory addressing ( pd78f9234) special function registers (sfr) 256 8 bits internal high-speed ram 256 8 bits flash memory 8,192 8 bits use prohibited direct addressing register indirect addressing based addressing sfr addressing short direct addressing ffffh ff00h feffh ff20h ff1fh fe00h fdffh fe20h fe1fh 2000h 1fffh 0000h chapter 3 cpu architecture user?s manual u17446ej5v0ud 33 3.2 processor registers the 78k0s/kb1+ provides the followi ng on-chip processor registers. 3.2.1 control registers the control registers have special f unctions to control the program sequenc e statuses and stack memory. the control registers include a pr ogram counter, a program stat us word, and a stack pointer. (1) program counter (pc) the program counter is a 16-bit r egister which holds the address info rmation of the next program to be executed. in normal operation, the pc is automat ically incremented according to the num ber of bytes of the instruction to be fetched. when a branch instruct ion is executed, immediate data or register contents are set. reset signal generation sets the reset vector tabl e values at addresses 0000h and 0001h to the program counter. figure 3-5. program counter configuration 0 15 pc14 pc15 pc pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (2) program status word (psw) the program status word is an 8-bit r egister consisting of various flags to be set/reset by instruction execution. program status word contents ar e stored in stack area upon interrupt request generation or push psw instruction execution and are re stored upon execution of the re ti and pop psw instructions. reset signal generation sets psw to 02h. figure 3-6. program status word configuration 70 ie z 0 ac 0 0 1 cy psw (a) interrupt enable flag (ie) this flag controls interrupt request acknowledge operations of the cpu. when ie = 0, the interrupt disabled (di) status is set. all interrupt requests are disabled. when ie = 1, the interrupt enabled (ei) status is set. interrupt reques t acknowledgment is controlled with an interrupt mask flag for various interrupt sources. this flag is reset to 0 upon di instruction executi on or interrupt acknowledgment and is set to 1 upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is set to 1. it is reset to 0 in all other cases. (c) auxiliary carry flag (ac) if the operation result has a carry from bi t 3 or a borrow at bit 3, this flag is set to 1. it is reset to 0 in all other cases. chapter 3 cpu architecture user?s manual u17446ej5v0ud 34 (d) carry flag (cy) this flag stores overflow and underfl ow that have occurred upon add/subtra ct instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruct ion execution. (3) stack pointer (sp) this is a 16-bit register to hold the start address of t he memory stack area. only the internal high-speed ram area can be set as the stack area (the stack area c annot be set except internal high-speed ram area). figure 3-7. stack pointer configuration 0 15 sp14 sp15 sp sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 the sp is decremented befor e writing (saving) to the stack me mory and is incremented after reading (restoring) from the stack memory. each stack operation saves/restores dat a as shown in figures 3-8 and 3-9. cautions 1. since generation of reset signal makes the sp contents undefined, be sure to initialize the sp before using the stack memory. 2. stack pointers can be set only to the hi gh-speed ram area, and only the lower 10 bits can be actually set. thus, if the stack pointer is specified to 0 ff00h, it is converted to 0fb00h in the high- speed ram area, since 0ff00h is in the sfr area and not in the high-speed ram area. when the value is actually pushed onto th e stack, 1 is subtracted from 0fb00h to become 0faffh, but since that value is not in the high-speed ram area, it is converted to 0feffh, which is the same value as wh en 0ff00h is set to the stack pointer. chapter 3 cpu architecture user?s manual u17446ej5v0ud 35 figure 3-8. data to be saved to stack memory interrupt psw pc15 to pc8 pc15 to pc8 pc7 to pc0 lower half register pairs sp sp _ 2 sp _ 2 call, callt instructions push rp instruction sp _ 1 sp sp sp _ 2 sp _ 2 sp _ 1 sp pc7 to pc0 sp _ 3 sp _ 2 sp _ 1 sp sp sp _ 3 upper half register pairs figure 3-9. data to be restored from stack memory reti instruction psw pc15 to pc8 pc15 to pc8 pc7 to pc0 lower half register pairs ret instruction pop rp instruction sp pc7 to pc0 upper half register pairs sp + 1 sp sp + 2 sp sp + 1 sp sp + 2 sp sp + 1 sp + 2 sp sp + 3 chapter 3 cpu architecture user?s manual u17446ej5v0ud 36 3.2.2 general-purpose registers a general-purpose register consists of eight 8-bit registers (x, a, c, b, e, d, l, and h). in addition each register being used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit register (ax, bc, de, and hl). registers can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). figure 3-10. general-purpo se register configuration (a) function names x 15 0 7 0 16-bit processing 8-bit processing hl de bc ax a c b e d l h (b) absolute names r0 15 0 7 0 16-bit processing 8-bit processing rp3 rp2 rp1 rp0 r1 r2 r3 r4 r5 r6 r7 chapter 3 cpu architecture user?s manual u17446ej5v0ud 37 3.2.3 special function registers (sfrs) unlike the general-purpose register s, each special function regist er has a special function. the special function registers are alloca ted to the 256-byte area ff00h to ffffh. the special function register s can be manipulated, like t he general-purpose registers, with operation, transfer, and bit manipulation instructions. manipulatable bit units (1 , 8, and 16) differ depending on the special function register type. each manipulation bit unit can be specified as follows. ? 1-bit manipulation describes a symbol reserved by the assembler for the 1- bit manipulation instructi on operand (sfr.bit). this manipulation can also be specified with an address and bit. ? 8-bit manipulation describes a symbol reserved by the assembler for the 8-bit manipulation instruct ion operand (sfr). this manipulation can also be specified with an address. ? 16-bit manipulation describes a symbol reserved by the assembler for the 16-bit manipulation instruct ion operand. when specifying an address, describe an even address. table 3-3 lists the special function r egisters. the meanings of the symbol s in this table are as follows: ? symbol indicates the addresses of the implement ed special function registers. it is defined as a reserved word in the ra78k0s, and is defined as an sfr variabl e using the #pragma sfr directive in the cc78k0s. t herefore, these symbols can be used as instruction operands if an assembler or integrated debugger is used. ? r/w indicates whether the special functi on register can be read or written. r/w: read/write r: read only w: write only ? number of bits manipulated simultaneously indicates the bit units (1, 8, and 16) in which the special function regi ster can be manipulated. ? after reset indicates the status of the special function register w hen a reset signal is generated. chapter 3 cpu architecture user?s manual u17446ej5v0ud 38 table 3-3. special function registers (1/4) bit no. number of bits manipulated simultaneously address symbol 7 6 5 4 3 2 1 0 r/w 1 8 16 after reset reference page ff00h p0 0 0 0 0 p03 p02 p01 p00 r/w note 1 ? 00h 68 ff01h ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ff02h p2 0 0 0 0 p23 p22 p21 p20 ? 00h 68 ff03h p3 0 0 0 p34 p33 p32 p31 p30 ? 00h 68 ff04h p4 p47 p46 p45 p44 p43 p42 p41 p40 r/w note 1 ? 00h 68 ff05h to ff0bh ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ff0ch p12 0 0 0 0 p123 p122 p121 p120 ? 00h 68 ff0dh p13 0 0 0 0 0 0 0 p130 r/w note 1 ? 00h 68 ff0eh cmp01 ? ? ? ? ? ? ? ? ? ? 00h 138 ff0fh cmp11 ? ? ? ? ? ? ? ? r/w ? ? 00h 138 ff10h mul 0l ? ? ? ? ? ? ? ? ? 220 ff11h mul 0h mu l0 ? ? ? ? ? ? ? ? ? undefined 220 ff12h ? ? ? ? ? ? ? ? ff13h tm00 ? ? ? ? ? ? ? ? r ? ? note 2 0000h 90 ff14h ? ? ? ? ? ? ? ? ff15h cr000 ? ? ? ? ? ? ? ? ? ? note 2 0000h 90 ff16h ? ? ? ? ? ? ? ? ff17h cr010 ? ? ? ? ? ? ? ? r/w ? ? note 2 0000h 92 ff18h ? ? ? ? ? ? ? ? ff19h adcr 0 0 0 0 0 0 ? ? ? ? note 2 170 ff1ah adcrh ? ? ? ? ? ? ? ? r ? ? undefined 171 ff1bh to ff21h ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ff20h pm0 1 1 1 1 pm03 pm02 pm01 pm00 r/w ? ffh 67 ff21h ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ff22h pm2 1 1 1 1 pm23 pm22 pm21 pm20 ? ffh 67, 171 ff23h pm3 1 1 1 1 pm33 pm32 pm31 pm30 ? ffh 67, 98 ff24h pm4 pm47 pm46 pm45 pm44 pm43 pm42 pm41 pm40 r/w ? ffh 67, 141, 197 ff25h to ff2bh ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ff2ch pm12 1 1 1 1 pm123 pm122 pm121 pm120 r/w ? ffh 67 ff2dh to ff2fh ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ff30h pu0 0 0 0 0 pu03 pu02 pu01 pu00 r/w ? 00h 70 ff31h ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ff32h pu2 0 0 0 0 pu23 pu22 pu21 pu20 ? 00h 70 ff33h pu3 0 0 0 0 pu33 pu32 pu31 pu30 r/w ? 00h 70 notes 1. only p34 is an input-only port. 2. a 16-bit access is possible only by the short direction addressing. chapter 3 cpu architecture user?s manual u17446ej5v0ud 39 table 3-3. special function registers (2/4) bit no. number of bits manipulated simultaneously address symbol 7 6 5 4 3 2 1 0 r/w 1 8 16 after reset reference page ff34h pu4 pu47 pu46 pu45 pu 44 pu43 pu42 pu41 pu40 r/w ? 00h 70 ff35h to ff3bh ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ff3ch pu12 0 0 0 0 pu123 0 0 pu120 r/w ? 00h 70 ff3dh to ff47h ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ff48h wdtm 0 1 1 wdcs 4 wdcs 3 wdcs 2 wdcs 1 wdcs 0 ? ? 67h 154 ff49h wdte ? ? ? ? ? ? ? ? ? ? 9ah 155 ff50h lvim chapter 3 cpu architecture user?s manual u17446ej5v0ud 40 table 3-3. special function registers (3/4) bit no. number of bits manipulated simultaneously address symbol 7 6 5 4 3 2 1 0 r/w 1 8 16 after reset reference page ff84h pmc2 0 0 0 0 pmc23 pmc22 pmc21 pmc20 r/w ? 00h 69, 171 ff85h to ff8bh ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ff8ch isc 0 0 0 0 0 0 isc1 isc0 r/w ? 00h 197 ff8dh to ff8fh ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ff90h asim6 chapter 3 cpu architecture user?s manual u17446ej5v0ud 41 table 3-3. special function registers (4/4) bit no. number of bits manipulated simultaneously address symbol 7 6 5 4 3 2 1 0 r/w 1 8 16 after reset reference page ffd0h mra0 ? ? ? ? ? ? ? ? ? ? 220 ffd1h mrb0 ? ? ? ? ? ? ? ? w ? ? undefined 220 ffd2h mulc0 0 0 0 0 0 0 0 chapter 3 cpu architecture user?s manual u17446ej5v0ud 42 3.3 instruction address addressing an instruction address is determined by the program counter (p c) contents. the pc contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an in struction to be fetched each time another instruction is executed. when a branch instruction is ex ecuted, the branch destination address information is set to the pc to branch by the following addressing (for details of eac h instruction, refer to 78k/0s series instructions user?s manual (u11047e) ). 3.3.1 relative addressing [function] the value obtained by adding 8-bit immediat e data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (p c) to branch. the displacement value is treated as signed two?s complement data (?128 to +127) and bit 7 becomes the sign bit. in other words, the range of branch in relative addressing is betw een ?128 and +127 of the start address of the following instruction. this function is carried out when the br $addr16 instruct ion or a conditional branch instruction is executed. [illustration] 15 0 pc 15 0 s 15 0 pc + 876 jdisp8 when s = 0, indicates that all bits are ?0?. ... pc is the start address of the next instruction of a br instruction. when s = 1, indicates that all bits are ?1?. chapter 3 cpu architecture user?s manual u17446ej5v0ud 43 3.3.2 immediate addressing [function] immediate data in the instructi on word is transferred to the pr ogram counter (pc) to branch. this function is carried out when the call !addr 16 and br !addr16 instruct ions are executed. call !addr16 and br !addr16 instru ctions can be used to branch to all the memory spaces. [illustration] in case of call !addr16 and br !addr16 instructions pc pc pc+1 pc+2 15 0 7 0 7 8 call or br low addr. high addr. 3.3.3 table indirect addressing [function] the table contents (branch des tination address) of the particular locati on to be addressed by the immediate data of an instruction code from bit 1 to bit 5 are tr ansferred to the program counter (pc) to branch. table indirect addressing is carried out when the callt [addr5] inst ruction is executed. this instruction can be used to branch to all the memory spaces according to the address stored in the me mory table 40h to 7fh. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address + 1 effective address 01 00000000 87 87 65 0 0 0 01 765 10 ta 4?0 instruction code chapter 3 cpu architecture user?s manual u17446ej5v0ud 44 3.3.4 register addressing [function] the register pair (ax) contents to be specified with an instruction word ar e transferred to the program counter (pc) to branch. this function is carried out when t he br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87 chapter 3 cpu architecture user?s manual u17446ej5v0ud 45 3.4 operand address addressing the following methods (addressing) are available to s pecify the register and memo ry to undergo manipulation during instruction execution. 3.4.1 direct addressing [function] the memory indicated by immediate data in an instruction word is directly addressed. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !0fe80h; when setting !addr16 to fe80h instruction code 0 0 1 0 1 0 0 1 op code 1 0 0 0 0 0 0 0 80h 1 1 1 1 1 1 1 0 feh [illustration] 70 op code addr16 (low) addr16 (high) memory chapter 3 cpu architecture user?s manual u17446ej5v0ud 46 3.4.2 short direct addressing [function] the memory to be manipulated in the fixed space is dire ctly addressed with the 8-bit data in an instruction word. the fixed space where this addressing is applied is t he 256-byte space fe20h to ff1fh (fe20h to feffh (internal high-speed ram) + ff00h to ff1fh (special function registers)). the sfr area where short direct addressi ng is applied (ff00h to ff1fh) is a par t of the total sfr area. in this area, ports which are frequently access ed in a program and a compare register of the timer counter are mapped, and these sfrs can be mani pulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an e ffective address is cleared to 0. when it is at 00h to 1fh, bit 8 is set to 1. see [illustration] below. [operand format] identifier description saddr label or fe20h to ff1fh immediate data saddrp label or fe20h to ff1fh i mmediate data (even address only) [description example] equ data1 0fe90h; data1 indicates fe90h in saddr area mov data1, #50h; when the immediate data to 50h instruction code 1 1 1 1 0 1 0 1 op code 1 0 0 1 0 0 0 0 90h (saddr-offset) 0 1 0 1 0 0 0 0 50h (immediate data) [illustration] 15 0 short direct memory effective address 1 111111 8 0 7 op code saddr-offset when 8-bit immediate data is 20h to ffh, = 0. when 8-bit immediate data is 00h to 1fh, = 1. chapter 3 cpu architecture user?s manual u17446ej5v0ud 47 3.4.3 special function register (sfr) addressing [function] a memory-mapped special function register (sfr) is addre ssed with the 8-bit immediat e data in an instruction word. this addressing is applied to the 256-byte space ff 00h to ffffh. however, sfrs mapped at ff00h to ff1fh are accessed with short direct addressing. [operand format] identifier description sfr special function register name [description example] mov pm0, a; when selecting pm0 for sfr instruction code 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 [illustration] 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1 chapter 3 cpu architecture user?s manual u17446ej5v0ud 48 3.4.4 register addressing [function] a general-purpose register is accessed as an operand. the general-purpose register to be acce ssed is specified with t he register specify c ode and functional name in the instruction code. register addressing is carried out when an instruction with the following operand forma t is executed. when an 8-bit register is specified, one of the eight registers is specified wit h 3 bits in the instruction code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl ?r? and ?rp? can be described with absolute names (r0 to r7 and rp0 to rp3) as well as function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl). [description example] mov a, c; when selecting the c register for r instruction code 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 1 register specify code incw de; when selecting the de register pair for rp instruction code 1 0 0 0 1 0 0 0 register specify code chapter 3 cpu architecture user?s manual u17446ej5v0ud 49 3.4.5 register indirect addressing [function] the memory is addressed with the contents of the r egister pair specified as an oper and. the register pair to be accessed is specified with t he register pair specify code in the instruction code. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [de], [hl] [description example] mov a, [de]; when selecting register pair [de] instruction code 0 0 1 0 1 0 1 1 [illustration] 15 0 8 d 7 e 0 7 7 0 a de the contents of addressed memory are transferred memory address specified by register pair de chapter 3 cpu architecture user?s manual u17446ej5v0ud 50 3.4.6 based addressing [function] 8-bit immediate data is added to the cont ents of the base register, that is, t he hl register pair, and the sum is used to address the memory. addition is performed by ex panding the offset data as a pos itive number to 16 bits. a carry from the 16th bit is ignored. this addre ssing can be carried out for all the memory spaces. [operand format] identifier description ? [hl+byte] [description example] mov a, [hl+10h]; when setting byte to 10h instruction code 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 [illustration] 16 0 h 7 8 l 0 7 7 0 a hl the contents of the memory addressed are transferred. memory +10 chapter 3 cpu architecture user?s manual u17446ej5v0ud 51 3.4.7 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subrout ine call, and return instructions are executed or the register is sav ed/restored upon interrupt request generation. stack addressing can be used to access t he internal high-speed ram area only. [description example] in the case of push de instruction code 1 0 1 0 1 0 1 0 [illustration] e fee0h sp sp fee0h fedfh fedeh d memory 0 7 fedeh user?s manual u17446ej5v0ud 52 chapter 4 port functions 4.1 functions of ports the 78k0s/kb1+ has the ports shown in figure 4-1, which can be used for va rious control operations. table 4-1 shows the functions of each port. in addition to digital i/o port functions , each of these ports has an alternat e function. for details, refer to chapter 2 pin functions . figure 4-1. port functions port 4 p40 port 13 p130 p00 port 0 p03 p20 port 2 p23 p30 port 3 p33 p34 p47 p120 p123 port 12 chapter 4 port functions user?s manual u17446ej5v0ud 53 table 4-1. port functions pin name i/o function after reset alternate- function pin p00 to p03 i/o port 0. 4-bit i/o port. can be set to input or output mode in 1-bit units. on-chip pull-up resistor can be connected by setting software. input ? p20 to p23 i/o port 2. 4-bit i/o port. can be set to input or output mode in 1-bit units. on-chip pull-up resistor can be connected by setting software. input ani0 to ani3 p30 ti000/intp0 p31 ti010/to00/ intp2 p32 ? p33 i/o can be set to input or output mode in 1- bit units. on-chip pull-up resistor can be connected by setting software. input ? p34 note input port 3 input only input reset note p40 ? p41 intp3 p42 toh1 p43 txd6/intp1 p44 rxd6 p45 ? p46 ? p47 i/o port 4. 8-bit i/o port. can be set to input or output mode in 1-bit units. on-chip pull-up resistor can be connected by setting software. input ? p120 ? p121 note x1 note p122 note x2 note p123 i/o port 12. 4-bit i/o port. can be set to input or output mode in 1-bit units. on-chip pull-up resistor can be connected only to p120 and p123 by setting software. input ? p130 output port 13. 1-bit output-only port. output ? note for settings of alternate function, refer to chapter 18 option byte . caution the p121/x1 and p122/x2 pins are pulled down during reset. remarks 1. p121 and p122 can be allocated when the high-spe ed internal oscillation is selected as the system clock. 2. p122 can be allocated when an external clock is selected as the system clock. chapter 4 port functions user?s manual u17446ej5v0ud 54 4.2 port configuration ports consist of the following hardware units. table 4-2. configuration of ports item configuration control registers port mode registers (pm0, pm2, pm3, pm4, pm12) port registers (p0, p2, p3, p4, p12, p13) port mode control register 2 (pmc2) pull-up resistor option registers (pu0, pu2, pu3, pu4, pu12) ports total: 26 (cmos i/o: 24, cmos input: 1, cmos output: 1) pull-up resistor total: 22 chapter 4 port functions user?s manual u17446ej5v0ud 55 4.2.1 port 0 port 0 is a 4-bit i/o port with an output latch. each bit of this port can be set to the input or output mode by using port mode register 0 (pm0). when the p00 to p03 pins are used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull- up resistor option register 0 (pu0). this port is also used as the analog input pins of the internal a/d converter. generation of reset signal sets port 0 to the input mode. figure 4-2 shows the block diagram of port 0. figure 4-2. block diagram of p00 to p03 p00 to p03 wr pu rd wr port wr pm pu00 to pu03 output latch (p00 to p03) pm00 to pm03 v dd p-ch pm0 p0 pu0 selector internal bus pu0: pull-up resistor option register 0 p0: port register 0 pm0: port mode register 0 rd: read signal wr : write signal chapter 4 port functions user?s manual u17446ej5v0ud 56 4.2.2 port 2 port 2 is a 4-bit i/o port with an output latch. each bit of this port can be set to the input or output mode by using port mode register 2 (pm2). when the p20 to p23 pins are used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull- up resistor option register 2 (pu2). this port is also used as the analog input pins of the internal a/d converter. generation of reset signal sets port 2 to the input mode. figure 4-2 shows the block diagram of port 2. figure 4-3. block diagram of p20 to p23 p20/ani0 to p23/ani3 wr pu rd pu20 to pu23 wr pm pm20 to pm23 v dd p-ch pu2 pmc2 pm2 wr port output latch (p20 to p23) pmc20 to pmc23 a/d converter internal bus selector wr pmc p2 pu2: pull-up resistor option register 2 p2: port register 2 pm2: port mode register 2 pmc2: port mode control register 2 rd: read signal wr : write signal chapter 4 port functions user?s manual u17446ej5v0ud 57 4.2.3 port 3 pins p30 to p33 constitute a 4-bit i/o port with an output la tch. each bit of this port can be set to the input or output mode by using port mode register 3 (pm3). when the p30 to p33 pins are used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 3 (pu3). the p30 and p31 pins are also used for both timer i/o and external interrupt request input pin functions. generation of reset signal sets port 3 to the input mode. p34 is a 1-bit input-only port. this pin is also used as a reset pin, and when the power is turned on, this is the reset function. for settings of alternate function, refer to chapter 18 option byte . when using p34 as input port, pull up the p34 pin by using external resistor. figures 4-4 to 4-7 show the block diagrams of port 3. figure 4-4. block diagram of p30 p30/ti000/intp0 wr pu rd wr port wr pm pu30 output latch (p30) pm30 v dd p-ch pu3 pm3 internal bus selector alternate function p3 pu3: pull-up resistor option register 3 p3: port register 3 pm3: port mode register 3 rd: read signal wr : write signal chapter 4 port functions user?s manual u17446ej5v0ud 58 figure 4-5. block diagram of p31 p31/ti010/to00/intp2 wr pu rd wr port wr pm pu31 output latch (p31) pm31 alternate function v dd p-ch pu3 pm3 internal bus selector alternate function p3 pu3: pull-up resistor option register 3 p3: port register 3 pm3: port mode register 3 rd: read signal wr : write signal chapter 4 port functions user?s manual u17446ej5v0ud 59 figure 4-6. block diagram of p32 and p33 p32, p33 wr pu rd wr port wr pm pu32, pu33 output latch (p32, p33) pm32, pm33 v dd p-ch pm3 p3 pu3 selector internal bus pu3: pull-up resistor option register 3 p3: port register 3 pm3: port mode register 3 rd: read signal wr : write signal figure 4-7. block diagram of p34 rd p34/reset option byte reset internal bus rd: read signal caution because the p34 pin functions al ternately as the reset pin, if it is used as an input port pin, the function to input an external r eset signal to the reset pin cannot be used. the function of the port is selected by the option byte. for details, refer to chapter 18 option byte. chapter 4 port functions user?s manual u17446ej5v0ud 60 also, since the option byte is refe renced after the reset release, if low level is input to the reset pin before the referencing, then the reset state is not released. wh en it is used as an input port pin, connect the pull-up resistor. 4.2.4 port 4 port 4 is an 8-bit i/o port with an output latc h. each bit of this port can be se t to the input or output mode by using port mode register 4 (pm4). when the p40 to p47 pins are used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull- up resistor option register 4 (pu4). the p41 to p44 pins can also be used for external in terrupt request input, serial interface data i/o, and timer output. generation of reset signal sets port 4 to the input mode. figures 4-8 to 4-11 show the block diagrams of port 4. figure 4-8. block diagra m of p40, p45 to p47 p40, p45 to p47 wr pu rd wr port wr pm pu40, pu45 to pu47 output latch (p40, p45 to p47) pm40, pm45 to pm47 v dd p-ch pu4 pm4 internal bus selector p4 pu4: pull-up resistor option register 4 p4: port register 4 pm4: port mode register 4 rd: read signal wr : write signal chapter 4 port functions user?s manual u17446ej5v0ud 61 figure 4-9. block diagram of p41 and p44 p41/intp3, p44/rxd6 wr pu rd wr port wr pm pu41, pu44 alternate function output latch (p41, p44) pm41, pm44 v dd p-ch pu4 pm4 internal bus selector p4 pu4: pull-up resistor option register 4 p4: port register 4 pm4: port mode register 4 rd: read signal wr : write signal chapter 4 port functions user?s manual u17446ej5v0ud 62 figure 4-10. blo ck diagram of p42 p42/toh1 wr pu rd wr port wr pm pu42 output latch (p42) pm42 alternate function v dd p-ch pm4 pu4 internal bus selector p4 pu4: pull-up resistor option register 4 p4: port register 4 pm4: port mode register 4 rd: read signal wr : write signal chapter 4 port functions user?s manual u17446ej5v0ud 63 figure 4-11. blo ck diagram of p43 p43/txd6/intp1 wr pu rd wr port wr pm pu43 output latch (p43) pm43 alternate function v dd p-ch pu4 pm4 internal bus selector alternate function p4 pu4: pull-up resistor option register 4 p4: port register 4 pm4: port mode register 4 rd: read signal wr : write signal 4.2.5 port 12 port 12 is a 4-bit i/o port with an output latch. each bit of this port can be set to the input or output mode by using port mode register 12 (pm12). when the p120 and p123 pins are used as an input port, an on-chip pull-up resistor can be connected by using pull-up re sistor option register 12 (pu12). the p121 and p122 pins are also used as the x1 and x2 pins of the system clock oscillator. the functions of the p121 and p122 pins differ, therefore, depending on the selected system clock os cillator. the following three system clock oscillators can be used. (1) high-speed internal oscillator the p121 and p122 pins can be used as i/o port pins. (2) crystal/ceram ic oscillator the p121 and p122 pins cannot be used as i/o port pi ns because they are used as the x1 and x2 pins. chapter 4 port functions user?s manual u17446ej5v0ud 64 (3) external clock input the p121 pin is used as the x1 pin to input an external clock, and therefore it cannot be used as an i/o port pin. the p122 pin can be used as an i/o port pin. the system clock oscillation is selected by the option byte. for details, refer to chapter 18 option byte . generation of reset signal sets port 12 to the input mode. figures 4-12 and 4-13 show the block diagrams of port 12. figure 4-12. block di agram of p120 and p123 p120, p123 wr pu rd wr port wr pm pu120, pu123 output latch (p120, p123) pm120, pm123 v dd p-ch pm12 pu12 internal bus selector p12 pu12: pull-up resistor option register 12 p12: port register 12 pm12: port mode register 12 rd: read signal wr : write signal chapter 4 port functions user?s manual u17446ej5v0ud 65 figure 4-13. block di agram of p121 and p122 p121/x1, p122/x2 rd wr port wr pm output latch (p121, p122) pm121, pm122 pm12 internal bus selector p12 pm12: port mode register 12 p12: port register 12 rd: read signal wr : write signal 4.2.6 port 13 this is a 1-bit output-only port. figure 4-14 shows the block diagram of port 13. figure 4-14. blo ck diagram of p130 rd output latch (p130) wr port p130 internal bus p13 p13: port register 13 rd: read signal wr : write signal remark when a reset is input, p130 outputs a low level. if p130 outputs a high level immediately after reset is released, the output signal of p130 can be used as a dummy cpu reset signal. chapter 4 port functions user?s manual u17446ej5v0ud 66 4.3 registers controlling port functions the ports are controlled by the follo wing four types of registers. ? port mode registers (pm0, pm2, pm3, pm4, pm12) ? port registers (p0, p2, p3, p4, p12, p13) ? port mode control register 2 (pmc2) ? pull-up resistor option registers (pu0, pu2, pu3, pu4, pu12) chapter 4 port functions user?s manual u17446ej5v0ud 67 (1) port mode registers (pm0, pm2, pm3, pm4, pm12) these registers are used to set the corresponding port to the input or output mode in 1-bit units. each port mode register can be set by a 1-bit or 8-bit memory manipulation instruction. generation of reset signal sets these registers to ffh. when a port pin is used as an alternate-function pin, se t its port mode register and output latch as shown in table 4-3. caution because p30, p31, and p4 3 are also used as external in terrupt pins, the corresponding interrupt request flag is set if each of these pins is set to the output mode and its output level is changed. to use the port pin in the output mode, therefore, set the corresponding interrupt mask flag to 1 in advance. figure 4-15. format of port mode register address: ff20h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm0 1 1 1 1 pm03 pm02 pm01 pm00 address: ff22h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm2 1 1 1 1 pm23 pm22 pm21 pm20 address: ff23h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm3 1 1 1 1 pm33 pm32 pm31 pm30 address: ff24h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm4 pm47 pm46 pm45 pm44 pm43 pm42 pm41 pm40 address: ff2ch after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm12 1 1 1 1 pm123 pm122 pm121 pm120 pmmn selection of i/o mode of pmn pin (m = 0, 2, 3, 4, or 12; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 4 port functions user?s manual u17446ej5v0ud 68 (2) port registers (p0, p2, p3, p4, p12, p13) these registers are used to write dat a to be output from the corresponding port pin to an external device connected to the chip. when a port register is read, the pin level is read in t he input mode, and the value of the output latch of the port is read in the output mode. p00 to p03, p20 to p23, p30 to p 34, p40 to p47, p120 to p123, and p130 are set by using a 1-bit or 8-bit memory manipulation instruction. generation of reset signal sets these registers to 00h. figure 4-16. format of port register address: ff00h after reset: 00h (output latch) r/w symbol 7 6 5 4 3 2 1 0 p0 0 0 0 0 p03 p02 p01 p00 address: ff02h after reset: 00h (output latch) r/w symbol 7 6 5 4 3 2 1 0 p2 0 0 0 0 p23 p22 p21 p20 address: ff03h after reset: 00h note (output latch) r/w note symbol 7 6 5 4 3 2 1 0 p3 0 0 0 p34 p33 p32 p31 p30 address: ff04h after reset: 00h (output latch) r/w symbol 7 6 5 4 3 2 1 0 p4 p47 p46 p45 p44 p43 p42 p41 p40 address: ff0ch after reset: 00h (output latch) r/w symbol 7 6 5 4 3 2 1 0 p12 0 0 0 0 p123 p122 p121 p120 address: ff0dh after reset: 00h (output latch) r/w symbol 7 6 5 4 3 2 1 0 p13 0 0 0 0 0 0 0 p130 m = 0, 2, 3, 4, 12, or 13; n = 0-7 pmn controls of output data (in output mode) input data read (in input mode) 0 output 0 input low level 1 output 1 input high level note because p34 is read-only, its reset value is undefined. chapter 4 port functions user?s manual u17446ej5v0ud 69 (3) port mode control register 2 (pmc2) this register specifies the port mode or a/d converter mode. each bit of the pmc2 register corresponds to eac h pin of port 2 and can be specified in 1-bit units. pmc2 is set by using a 1-bit or 8-bit memory manipulation instruction. generation of reset signal sets pmc2 to 00h. figure 4-17. format of port mode control register 2 address: ff84h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pmc2 0 0 0 0 pmc23 pmc22 pmc21 pmc20 pmc2n specification of operation mode (n = 0 to 3) 0 port mode 1 a/d converter mode caution when pmc20 to pmc23 are set to 1, the p20/ani 0 to p23/ani3 pins cannot be used as port pins. moreover, be sure to set the pull-up r esistor option registers (pu20 to pu23) to 0 for the pins set to a/d converter mode. table 4-3. setting of port mode register, port regi ster (output latch), and port mode control register when alternate function is used alternate-function pin port name name i/o pm p pmc2n (n = 0 to 3) p20 to p23 ani0 to ani3 input 1 1 ti000 input 1 ? p30 intp0 input 1 ? to00 output 0 0 ? ti010 input 1 ? p31 intp2 input 1 ? p41 intp3 input 1 ? p42 toh1 output 0 0 ? txd6 output 0 1 ? p43 intp1 input 1 ? p44 rxd6 input 1 ? remark : don?t care pm : port mode register, p : port register (output latch of port) pmc2 : port mode control register chapter 4 port functions user?s manual u17446ej5v0ud 70 (4) pull-up resistor option register s (pu0, pu2, pu3, pu4, and pu12) these registers are used to specify wh ether an on-chip pull-up resistor is connected to p00 to p03, p20 to p23, p30 to p33, p40 to p47, p120, and p123. by se tting pu0, pu2, pu3, pu4, or pu12, an on-chip pull-up resistor can be connected to the port pin corresponding to the bit of pu0, pu2, pu3, pu4, or pu12. pu0, pu2, pu3, pu4, and pu12 are set by using a 1-bit or 8-bit memory manipulation instruction. generation of reset signal set these registers to 00h. figure 4-18. format of pull-up resistor option register address: ff30h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pu0 0 0 0 0 pu03 pu02 pu01 pu00 address: ff32h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pu2 0 0 0 0 pu23 pu22 pu21 pu20 address: ff33h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pu3 0 0 0 0 pu33 p32 pu31 pu30 address: ff34h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pu4 pu47 pu46 pu45 pu44 pu43 pu42 pu41 pu40 address: ff3ch after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pu12 0 0 0 0 pu123 0 0 pu120 pumn selection of connection of on-chip pull-up resistor of pmn (m = 0, 2, 3, 4, or 12; n = 0 to 7) 0 does not connect on-chip pull-up resistor 1 connects on-chip pull-up resistor chapter 4 port functions user?s manual u17446ej5v0ud 71 4.4 operation of port function the operation of a port differs, as follows , depending on the setting of the i/o mode. caution although a 1-bit memory ma nipulation instruction manipulates 1 bit, it accesses a port in 8-bit units. therefore, the contents of the output latch of a pin in the input mode, even if it is not subject to manipulation by the instruction, are undefined in a port with a mixture of inputs and outputs. 4.4.1 writing to i/o port (1) in output mode a value can be written to the output latch by a transfer inst ruction. in addition, the da ta of the output latch is output from the pin. once data is wri tten to the output latch, it is retained until new data is written to the output latch. reset signal generation clears the data in the output latch. (2) in input mode a value can be written to t he output latch by a transfer instruction. because the output buffer is off, however, the pin status remains unchanged. once data is written to the output latch, it is re tained until new data is wri tten to the output latch. reset signal generation clears the data in the output latch. 4.4.2 reading from i/o port (1) in output mode the data of the output latch can be r ead by a transfer instruction. the contents of the out put latch remain unchanged. (2) in input mode the pin status can be read by a trans fer instruction. the data of the output latch remains unchanged. 4.4.3 operations on i/o port (1) in output mode an operation is performed on the content s of the output latch and t he result is written to the output latch. the data of the output latch is output from the pin. once data is written to the output latch, it is re tained until new data is wri tten to the output latch. reset signal generation clears the data in the output latch. (2) in input mode the pin level is read and an operation is performed on its data. the operation result is written to the output latch. however, the pin status remains unch anged because the output buffer is off. reset signal generation clears the data in the output latch. user?s manual u17446ej5v0ud 72 chapter 5 clock generators 5.1 functions of clock generators the clock generators include a circuit that generates a clock (system clock) to be supplied to the cpu and peripheral hardware, and a circuit that generates a clock (interval time gen eration clock) to be supplied to the watchdog timer and 8-bit timer h1 (tmh1). 5.1.1 system clock oscillators the following three types of system clock oscillators are used. ? high-speed internal oscillator this circuit internally oscillates a clock of 8 mhz (typ.). its oscillation can be stopp ed by execution of the stop instruction. if the high-speed internal oscillator is selected to suppl y the system clock, the x1 an d x2 pins can be used as i/o port pins. ? crystal/ceramic oscillator this circuit oscillates a clock with a crystal/ceramic oscillator connected across the x1 and x2 pins. it can oscillate a clock of 2 to 10 mhz. oscillation of this ci rcuit can be stopped by executio n of the stop instruction. ? external clock input circuit this circuit supplies a clock from an external ic to the x1 pin. a clock of 2 to 10 mhz can be supplied. internal clock supply can be stopped by exec ution of the stop instruction. if the external clock input is selected as the syst em clock, the x2 pin can be used as an i/o port pin. the system clock source is se lected by using the option byte. for details, refer to chapter 18 option byte . when using the x1 and x2 pins as i/o port pins, refer to chapter 4 port functions for details. 5.1.2 clock oscillator for interval time generation the following circuit is used as a clock oscillator for interval time generation. ? low-speed internal oscillator this circuit oscillates a clock of 240 khz (typ.). its oscillation can be stopped by using the low-speed internal oscillation mode register (lsrcm) when it is specified by the option byte t hat its oscillation can be stopped by software. chapter 5 clock generators user?s manual u17446ej5v0ud 73 5.2 configuration of clock generators the clock generators consist of the following hardware. table 5-1. configuration of clock generators item configuration control registers processor clock control register (pcc) preprocessor clock control register (ppcc) low-speed internal oscillation mode register (lsrcm) oscillation stabilization time select register (osts) oscillators crystal/ceramic oscillator high-speed internal oscillator external clock input circuit low-speed internal oscillator chapter 5 clock generators user?s manual u17446ej5v0ud 74 figure 5-1. block diagra m of clock generators x1/p121 x2/p122 pcc1 c p u stop ppcc1 ppcc0 osts1 osts0 lsrstop controller selector cpu clock (f cpu ) internal bus internal bus oscillation stabilization time select register (osts) preprocessor clock control register (ppcc) processor clock control register (pcc) system clock oscillation stabilization time counter selector prescaler clock to peripheral hardware (f xp ) 8-bit timer h1, watchdog timer option byte 1: cannot be stopped. 0: can be stopped. low-speed internal oscillation mode register (lsrcm) low-speed internal oscillator prescaler system clock oscillator note external clock input crystal/ceramic oscillation high-speed internal oscillation watchdog timer f x f x 2 f xp 2 2 f xp f x 2 2 f rl note select the high-speed internal oscillator, crystal/ceram ic oscillator, or external clock input as the system clock source by using the option byte. chapter 5 clock generators user?s manual u17446ej5v0ud 75 5.3 registers controlling clock generators the clock generators are controlled by the following four registers. ? processor clock control register (pcc) ? preprocessor clock control register (ppcc) ? low-speed internal oscillation mode register (lsrcm) ? oscillation stabilization time select register (osts) (1) processor clock control register (pcc) an d preprocessor clock control register (ppcc) these registers are used to specify t he division ratio of the system clock. pcc and ppcc are set by using a 1-bit or 8-bit memory manipulation instruction. generation of reset signal sets pcc and ppcc to 02h. figure 5-2. format of processor clock control register (pcc) address: fffbh after reset: 02h r/w symbol 7 6 5 4 3 2 1 0 pcc 0 0 0 0 0 0 pcc1 0 figure 5-3. format of preprocesso r clock control register (ppcc) address: fff3h after reset: 02h r/w symbol 7 6 5 4 3 2 1 0 ppcc 0 0 0 0 0 0 ppcc1 ppcc0 ppcc1 ppcc0 pcc1 selection of cpu clock (f cpu ) 0 0 0 f x 0 1 0 f x /2 note 1 0 0 1 f x /2 2 1 0 0 f x /2 2 note 2 0 1 1 f x /2 3 note 1 1 0 1 f x /2 4 note 2 other than above setting prohibited notes 1. if ppcc = 01h, the clock (f xp ) supplied to the peripheral hardware is f x /2. 2. if ppcc = 02h, the clock (f xp ) supplied to the peripheral hardware is f x /2 2 . chapter 5 clock generators user?s manual u17446ej5v0ud 76 the fastest instruction of t he 78k0s/kb1+ is executed in two cpu clocks. therefore, the relationship between the cpu clock (f cpu ) and the minimum instruction execution time is as shown in table 5-2. table 5-2. relationship between cpu clo ck and minimum instruction execution time minimum instruction execution time: 2/f cpu cpu clock (f cpu ) note high-speed internal oscillation clock (at 8.0 mhz (typ.)) crystal/ceramic oscillation clock or external clock input (at 10.0 mhz) f x 0.25 s 0.2 s f x /2 0.5 s 0.4 s f x /2 2 1.0 s 0.8 s f x /2 3 2.0 s 1.6 s f x /2 4 4.0 s 3.2 s note the cpu clock (high-speed internal oscillation clock, crystal/ceramic oscillation clock, or external clock input) is selected by the option byte. (2) low-speed internal osc illation mode register (lsrcm) this register is used to select t he operation mode of the low-speed inte rnal oscillator (240 khz (typ.)). this register is valid when it is specified by the option byte that the low-speed internal oscillator can be stopped by software. if it is specified by the option byte that the low-speed internal oscillator cannot be stopped by software, setting of this register is invalid, and the low- speed internal oscillator continues oscillating. in addition, the source clock of wdt is fixed to the low-sp eed internal oscillator. for details, refer to chapter 9 watchdog timer . lsrcm can be set by using a 1-bit or 8-bit memory manipulation instruction. generation of reset signal sets lsrcm to 00h. figure 5-4. format of low-speed intern al oscillation mode register (lsrcm) address: ff58h after reset: 00h r/w symbol 7 6 5 4 3 2 1 <0> lsrcm 0 0 0 0 0 0 0 lsrstop lsrstop oscillation/stop of low-speed internal oscillator 0 low-speed internal oscillates 1 low-speed internal oscillator stops chapter 5 clock generators user?s manual u17446ej5v0ud 77 (3) oscillation stabilization time select register (osts) this register is used to select oscill ation stabilization time of the clock su pplied from the oscillator when the stop mode is released. the wait time set by osts is valid only when the crystal/ceramic oscillation clock is selected as the system clock and after the stop mode is released. if the high-speed internal oscillator or external clock input is selected as the system clock source, no wait time elapses. the system clock oscillator and the oscill ation stabilization time that elapses after power application or release of reset are selected by the option byte. for details, refer to chapter 18 option byte . osts is set by using an 8-bit me mory manipulation instruction. figure 5-5. format of oscillation stabiliz ation time select register (osts) address: fff4h after reset: undefined r/w symbol 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 0 osts1 osts0 osts1 osts0 selection of oscillation stabilization time 0 0 2 10 /f x (102.4 s) 0 1 2 12 /f x (409.6 s) 1 0 2 15 /f x (3.27 ms) 1 1 2 17 /f x (13.1 ms) cautions 1. to set and then release the stop mode , set the oscillation stabil ization time as follows. expected oscillation stab ilization time of resonator oscillation stabilization time set by osts 2. the wait time after the st op mode is released does not incl ude the time from the release of the stop mode to the start of clock oscilla tion (?a? in the figure below), regardless of whether stop mode was released by reset signal generation or in terrupt generation. stop mode is released voltage waveform of x1 pin a 3. the oscillation stabilization time that elapses on power applicatio n or after release of reset is selected by the option byte . for details, refer to chapter 18 option byte. remarks 1. ( ): f x = 10 mhz 2. determine the oscillation stabilization time of t he resonator by checking the characteristics of the resonator to be used. chapter 5 clock generators user?s manual u17446ej5v0ud 78 5.4 system clock oscillators the following three types of system clock oscillators are available. ? high-speed internal oscillator: internally oscillates a clock of 8 mhz (typ.). ? crystal/ceramic oscillator: oscillates a clock of 2 to 10 mhz. ? external clock input circuit: supplies a clock of 2 to 10 mhz to the x1 pin. 5.4.1 high-speed internal oscillator the 78k0s/kb1+ includes a high-speed internal oscillator (8 mhz (typ.)). if the high-speed internal oscillation is selected by the opt ion byte as the clock source, the x1 and x2 pins can be used as i/o port pins. for details of the option byte, refer to chapter 18 option byte . for details of i/o ports, refer to chapter 4 port functions . 5.4.2 crystal/ceram ic oscillator the crystal/ceramic oscillator oscillates using a cryst al or ceramic resonator connected between the x1 and x2 pins. if the crystal/ceramic oscillator is sele cted by the option byte as the system clock source, the x1 and x2 pins are used as crystal or ceramic resonator connection pins. for details of the option byte, refer to chapter 18 option byte . for details of i/o ports, refer to chapter 4 port functions . figure 5-6 shows the external circuit of the crystal/ceramic oscillator. figure 5-6. external circuit of crystal/ceramic oscillator v ss x1 x2 crystal resonator or ceramic resonator caution when using the crystal/ceram ic oscillator, wire as follows in the area enclosed by the broken lines in figure 5-6 to avoid an ad verse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lin es. do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor th e same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. chapter 5 clock generators user?s manual u17446ej5v0ud 79 figure 5-7 shows examples of incorrect resonator connection. figure 5-7. examples of incorre ct resonator connection (1/2) (a) too long wiring of connected circuit (b) crossed signal lines v ss x1 x2 v ss x1 x2 port (c) wiring near high fluctuating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates.) v ss x1 x2 high current v ss x1 x2 port v dd ab c high current chapter 5 clock generators user?s manual u17446ej5v0ud 80 figure 5-7. examples of incorre ct resonator connection (2/2) (e) signals are fetched v ss x1 x2 5.4.3 external clock input circuit this circuit supplies a clock from an external ic to the x1 pin. if external clock input is selected by the option byte as the system clock source, the x2 pin can be used as an i/o port pin. for details of the option byte, refer to chapter 18 option byte . for details of i/o ports, refer to chapter 4 port functions . 5.4.4 prescaler the prescaler divides the clock (f x ) output by the system clock osc illator to gener ate a clock (f xp ) to be supplied to the peripheral hardware. it also divides the clock to peripheral hardware (f xp ) to generate a clock to be supplied to the cpu. remark the clock output by the oscillat or selected by the option byte (h igh-speed internal oscillator, crystal/ceramic oscillator, or external clock input circui t) is divided. for details of the option byte, refer to chapter 18 option byte . chapter 5 clock generators user?s manual u17446ej5v0ud 81 5.5 operation of cpu clock generator a clock (f cpu ) is supplied to the cpu from the system clock (f x ) oscillated by one of the following three types of oscillators. ? high-speed internal oscillator: internally oscillates a clock of 8 mhz (typ.). ? crystal/ceramic oscillator: oscillates a clock of 2 to 10 mhz. ? external clock input circuit: supplies a clock of 2 to 10 mhz to x1 pin. the system clock oscillator is sele cted by the option byte. for deta ils of the option byte, refer to chapter 18 option byte . (1) high-speed internal oscillator when the high-speed internal oscillation is select ed by the option byte, the following is possible. ? shortening of start time if the high-speed internal oscillator is selected as the os cillator, the cpu can be star ted without having to wait for the oscillation st abilization time of the system clock. ther efore, the start time can be shortened. ? improvement of expandability if the high-speed internal oscillator is selected as the o scillator, the x1 and x2 pi ns can be used as i/o port pins. for details, refer to chapter 4 port functions . figures 5-8 and 5-9 show the timing chart and status transition diagram of the default start by the high-speed internal oscillation. remark when the high-speed internal oscillation is used, the clock accuracy is 5%. figure 5-8. timing chart of default st art by high-speed internal oscillation high-speed internal oscillation clock pcc = 02h, ppcc = 02h (a) (b) h reset internal reset system clock cpu clock option byte is read. system clock is selected. (operation stops note ) v dd note operation stop time is 277 s (min.), 544 s (typ.), and 1.075 ms (max.). chapter 5 clock generators user?s manual u17446ej5v0ud 82 (a) the internal reset signal is generated by the power- on-clear function on power applic ation, the option byte is referenced after reset, and the system clock is selected. (b) the option byte is referenced and the system clock is selected. then the high-speed internal oscillation clock operates as the system clock. figure 5-9. status transition of defaul t start by high-speed internal oscillation halt instruction stop instruction start with pcc = 02h, ppcc = 02h halt stop interrupt reset signal interrupt power application reset by power-on-clear high-speed internal oscillator selected by option byte clock division ratio variable during cpu operation v dd > 2.1 v (typ.) remark pcc: processor clock control register ppcc: preprocessor clock control register (2) crystal/ceram ic oscillator if crystal/ceramic oscillation is selected by the option byte, a clock frequency of 2 to 10 mhz can be selected and the accuracy of processing is improved because the frequ ency deviation is small, as compared with high-speed internal oscillation (8 mhz (typ.)). figures 5-10 and 5-11 show the timing chart and status transition diagram of default st art by the crystal/ceramic oscillator. chapter 5 clock generators user?s manual u17446ej5v0ud 83 figure 5-10. timing chart of default start by crystal/ceramic oscillator v dd crystal/ceramic oscillator clock pcc = 02h, ppcc = 02h (a) (b) (c) h reset system clock internal reset cpu clock option byte is read. system clock is selected. (operation stops note 1 ) clock oscillation stabilization time note 2 notes 1. operation stop time is 276 s (min.), 544 s (typ.), and 1.074 ms (max.). 2. the clock oscillation stabilization time for default star t is selected by the option byte. for details, refer to chapter 18 option byte . the oscillation stabilization time that elapses after the stop mode is released is selected by the oscillation stabilization time select register (osts). (a) the internal reset signal is generated by the power -on-clear function on power applic ation, the option byte is referenced after reset, and the system clock is selected. (b) after the high-speed internal oscillation clock is generated, the option byte is referenced and the system clock is selected. in th is case, the crystal/ceramic oscillator clock is selected as the system clock. (c) if the system clock is the crystal/ceramic oscillator clock, it starts operating as the cpu clock after clock oscillation is stabilized. the wait time is selected by the option byte. for details, refer to chapter 18 option byte . chapter 5 clock generators user?s manual u17446ej5v0ud 84 figure 5-11. status transition of defa ult start by crysta l/ceramic oscillation halt stop halt instruction stop instruction v dd > 2.1 v (typ.) start with pcc = 02h, ppcc = 02h interrupt reset signal interrupt power application clock division ratio variable during cpu operation wait for clock oscillation stabilization crystal/ceramic oscillation selected by option byte reset by power-on-clear remark pcc: processor clock control register ppcc: preprocessor clock control register (3) external clock input circuit if external clock input is selected by t he option byte, the following is possible. ? high-speed operation the accuracy of processing is improved as compared with high-speed internal oscillation (8 mhz (typ.)) because an oscillation frequency of 2 to 10 mhz can be se lected and an external clock with a small frequency deviation can be supplied. ? improvement of expandability if the external clock input circuit is selected as the o scillator, the x2 pin can be used as an i/o port pin. for details, refer to chapter 4 port functions . figures 5-12 and 5-13 show the timing chart and status tr ansition diagram of default start by external clock input. chapter 5 clock generators user?s manual u17446ej5v0ud 85 figure 5-12. timing of default start by external clock input v dd (a) (b) external clock input pcc = 02h, ppcc = 02h h reset system clock internal reset cpu clock option byte is read. system clock is selected. (operation stops note ) note operation stop time is 277 s (min.), 544 s (typ.), and 1.075 ms (max.). (a) the internal reset signal is generated by the power -on-clear function on power applic ation, the option byte is referenced after reset, and the system clock is selected. (b) the option byte is referenced and the system clock is selected. then the exte rnal clock operates as the system clock. figure 5-13. status transition of de fault start by external clock input halt stop halt instruction stop instruction v dd > 2.1 v (typ.) start with pcc = 02h, ppcc = 02h interrupt reset signal interrupt power application reset by power-on-clear external clock input selected by option byte clock division ratio variable during cpu operation remark pcc: processor clock control register ppcc: preprocessor clock control register chapter 5 clock generators user?s manual u17446ej5v0ud 86 5.6 operation of clock generator s upplying clock to peripheral hardware the following two types of clocks are supplied to the peripheral hardware. ? clock to peripheral hardware (f xp ) ? low-speed internal oscillation clock (f rl ) (1) clock to peripheral hardware the clock to the peripheral hardware is supplied by dividing the system clock (f x ). the division ratio is selected by the pre-processor clock control register (ppcc). three types of frequencies are selectable: ?f x ?, ?f x /2?, and ?f x /2 2 ?. table 5-3 lists the clocks supplied to the peripheral hardware. table 5-3. clocks to peripheral hardware ppcc1 ppcc0 selection of clock to peripheral hardware (f xp ) 0 0 f x 0 1 f x /2 1 0 f x /2 2 1 1 setting prohibited (2) low-speed internal oscillation clock the low-speed internal oscillator of the clock oscillator fo r interval time generation is always started after release of reset, and oscillates at 240 khz (typ.). it can be specified by the option byte whether the low- speed internal oscillator can or cannot be stopped by software. if it is specified that the low-speed internal oscillator can be stopped by software, oscillation can be started or stopped by using the low-speed internal oscillation mode register (l srcm). if it is specified that it cannot be stopped by software, the clock source of wdt is fixed to the low-speed internal oscillation clock (f rl ). the low-speed internal oscillator is independent of the cpu clock. if it is used as the source clock of wdt, therefore, a hang-up can be detected even if the cpu clock is stopped. if the low-speed internal oscillator is used as a count clock source of 8-bit timer h1, 8-bi t timer h1 can operate even in the standby status. table 5-4 shows the operation stat us of the low-speed internal oscillator w hen it is selected as the source clock of wdt and the count clock of 8-bit timer h1. figure 5-14 s hows the status transition of the low-speed internal oscillator. table 5-4. operation status of low-speed internal oscillator option byte setting cpu status wdt status tmh1 status lsrstop = 1 stopped stopped lsrstop = 0 operation mode operates operates lsrstop = 1 stopped stopped can be stopped by software lsrstop = 0 standby stopped operates operation mode cannot be stopped standby operates chapter 5 clock generators user?s manual u17446ej5v0ud 87 figure 5-14. status transition of low-speed internal oscillation lsrstop = 0 cannot be stopped can be stopped clock source of wdt is selected by software note clock source of wdt is fixed to f rl low-speed internal oscillator can be stopped low-speed internal oscillator cannot be stopped low-speed internal oscillator stops lsrstop = 1 reset signal power application reset by power-on-clear select by option byte if low-speed internal oscillator can be stopped or not v dd > 2.1 v (typ.) note the clock source of the watchdog timer (wdt) is selected from f x or f rl , or it may be stopped. for details, refer to chapter 9 watchdog timer . user?s manual u17446ej5v0ud 88 chapter 6 16-bit timer/event counter 00 6.1 functions of 16-bit timer/event counter 00 16-bit timer/event counter 00 has the following functions. (1) interval timer 16-bit timer/event counter 00 generates interr upt requests at the preset time interval. ? number of counts: 2 to 65536 (2) external event counter 16-bit timer/event counter 00 can measure the number of pulses with a high-/low-level width of valid level pulse width or more of a signal input externally. ? valid level pulse width: 2/f xp or more (3) pulse width measurement 16-bit timer/event counter 00 can measure the pulse width of an externally input signal. ? valid level pulse width: 2/f xp or more (4) square-wave output 16-bit timer/event counter 00 can output a square wave with any selected frequency. ? cycle: (2 to 65536) 2 count clock cycle (5) ppg output 16-bit timer/event counter 00 can output a squar e wave that have arbitrary cycle and pulse width. ? 1 < pulse width < cycle 65536 (6) one-shot pulse output 16-bit timer/event counter 00 can output a one-shot pulse for which out put pulse width can be set to any desired value. chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 89 6.2 configuration of 16-bi t timer/event counter 00 16-bit timer/event counter 00 cons ists of the following hardware. table 6-1. configuration of 16-bit timer/event counter 00 item configuration timer counter 16-bit timer counter 00 (tm00) register 16-bit timer capture/compare registers 000, 010 (cr000, cr010) timer input ti000, ti010 timer output to00, output controller control registers 16-bit timer mode control register 00 (tmc00) capture/compare control register 00 (crc00) 16-bit timer output control register 00 (toc00) prescaler mode register 00 (prm00) port mode register 3 (pm3) port register 3 (p3) figure 6-1 shows a block diagram of these counters. figure 6-1. block diagram of 16-bit timer/event counter 00 internal bus capture/compare control register 00 (crc00) ti010/to00/ intp2/p31 f xp f xp /2 2 f xp /2 8 f x ti000/intp0/p30 prescaler mode register 00 (prm00) 2 prm001 prm000 crc002 16-bit timer capture/compare register 010 (cr010) match match 16-bit timer counter 00 (tm00) clear noise elimi- nator crc002 crc001 crc000 inttm000 to00/ti010/ intp2/p31 inttm010 16-bit timer output control register 00 (toc00) 16-bit timer mode control register 00 (tmc00) internal bus tmc003 tmc002 tmc001 ovf00 toc004 lvs00 lvr00 toc001 toe00 selector 16-bit timer capture/compare register 000 (cr000) selector selector selector noise elimi- nator noise elimi- nator output controller ospe00 ospt00 output latch (p31) pm31 cr010 chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 90 (1) 16-bit timer counter 00 (tm00) tm00 is a 16-bit read-only regist er that counts count pulses. the counter is incremented in synchroni zation with the rising edge of the count clock. if the count value is read during operation, input of t he count clock is temporarily stopped, and t he count value at that point is read. figure 6-2. format of 16-bit timer counter 00 (tm00) tm00 symbol ff13h ff12h address: ff12h, ff13h after reset: 0000h r 7654321076543210 the count value is reset to 0000h in the following cases. <1> at reset signal generation <2> if tmc003 and tmc002 are cleared <3> if the valid edge of ti000 is input in the clear & start mode entered by inputting the valid edge of ti000 <4> if tm00 and cr000 match in the clear & star t mode entered on a match between tm00 and cr000 <5> if ospt00 is set to 1 in the one-shot pulse output mode cautions 1. even if tm00 is read, the value is not captured by cr010. 2. when tm00 is read, count misses do not occu r, since the input of the count clock is temporarily stopped and then resumed after the read. (2) 16-bit timer capture/comp are register 000 (cr000) cr000 is a 16-bit register which has the functions of both a capture register and a compare register. whether it is used as a capture register or as a compare register is set by bit 0 (crc000) of capture/compare control register 00 (crc00). cr000 is set by 16-bit memory manipulation instruction. reset signal generation clears this register to 0000h. figure 6-3. format of 16-bit timer ca pture/compare register 000 (cr000) cr000 symbol ff15h ff14h address: ff14h, ff15h after reset: 0000h r/w 7654321076543210 ? when cr000 is used as a compare register the value set in cr000 is constantly compared with the 16-bit timer/counter 00 (tm 00) count value, and an interrupt request (inttm000) is generat ed if they match. it can also be us ed as the register that holds the interval time then tm00 is set to interval timer operation. chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 91 ? when cr000 is used as a capture register it is possible to select the valid edge of the ti000 pi n or the ti010 pin as the c apture trigger. setting of the ti000 or ti010 valid edge is perfo rmed by means of prescaler mode register 00 (prm00) (refer to table 6- 2 ). table 6-2. cr000 capture trigger and valid edges of ti000 and ti010 pins (1) ti000 pin valid edge selected as captu re trigger (crc001 = 1, crc000 = 1) cr000 capture trigger ti000 pin valid edge es010 es000 falling edge rising edge 0 1 rising edge falling edge 0 0 no capture operation both rising and falling edges 1 1 (2) ti010 pin valid edge selected as captu re trigger (crc001 = 0, crc000 = 1) cr000 capture trigger ti010 pin valid edge es110 es100 falling edge falling edge 0 0 rising edge rising edge 0 1 both rising and falling edges both rising and falling edges 1 1 remarks 1. setting es010, es000 = 1, 0 and es110, es100 = 1, 0 is prohibited. 2. es010, es000: bits 5 and 4 of prescaler mode register 00 (prm00) es110, es100: bits 7 and 6 of prescaler mode register 00 (prm00) crc001, crc000: bits 1 and 0 of captur e/compare control register 00 (crc00) cautions 1. set cr000 to other than 0000h in the clear & start mode entered on match between tm00 and cr000. this means a 1-pulse count oper ation cannot be performed when this register is used as an external event counter. however, in the free-running mode and in the clear & start mode using the valid edge of ti000 pin, if cr000 is set to 0000h, an interrupt request (inttm000) is generated when cr000 changes from 0000h to 0001h following overflow (ffffh). 2. if the new value of cr000 is less than th e value of 16-bit timer counter 0 (tm00), tm00 continues counting, overflows, and then starts counting from 0 again. if the new value of cr000 is less than the old value , therefore, the timer must be reset to be restarted after the value of cr000 is changed. 3. the value of cr000 after 16-bit timer/ event counter 00 has stopped is not guaranteed. 4. the capture operation may not be perfo rmed for cr000 set in compare mode even if a capture trigger is input. 5. when using p31 as the input pin (ti010) of the valid edge, it cannot be used as a timer output pin (to00). when using p31 as the time r output pin (to00), it cannot be used as the input pin (ti010) of the valid edge. 6. if the register read period and the input of the capture trigger conflict when cr000 is used as a capture register, the capture trigge r input takes precedence and the read data is undefined. also, if the count stop of the timer and the input of the capture trigger conflict, the capture trigger is undefined. chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 92 caution 7. changing the cr000 setting during tm 00 operation may cause a malfunction. to change the setting, refer to 6.5 cautions related to 16-bit timer/event counter 00 (17) changing compare register during timer operation. (3) 16-bit timer capture/comp are register 010 (cr010) cr010 is a 16-bit register which has the functions of both a capture register and a compare register. whether it is used as a capture register or a compare register is set by bit 2 (crc002) of capture/compare control register 00 (crc00). cr010 is set by 16-bit memory manipulation instruction. reset signal generation clears cr010 to 0000h. figure 6-4. format of 16-bit timer ca pture/compare register 010 (cr010) cr010 symbol ff17h ff16h address: ff16h, ff17h after reset: 0000h r/w 7654321076543210 ? when cr010 is used as a compare register the value set in cr010 is constantly compared with the 16-bit timer count er 00 (tm00) count value, and an interrupt request (inttm010) is generated if they match. ? when cr010 is used as a capture register it is possible to select the valid edge of the ti000 pin as the capture trigger. the ti000 valid edge is set by means of prescaler mode register 00 (prm00) (refer to table 6-3 ). table 6-3. cr010 capture trigger and valid edge of ti000 pin (crc002 = 1) cr010 capture trigger ti000 pin valid edge es010 es000 falling edge falling edge 0 0 rising edge rising edge 0 1 both rising and falling edges both rising and falling edges 1 1 remarks 1. setting es010, es000 = 1, 0 is prohibited. 2. es010, es000: bits 5 and 4 of prescaler mode register 00 (prm00) crc002: bit 2 of capture/com pare control register 00 (crc00) cautions 1. in the free-running mode and in the cl ear & start mode using the valid edge of the ti000 pin, if cr010 is set to 0000h, an interrupt request (inttm 010) is generated when cr010 changes from 0000h to 0001h following overflow (ffffh). 2. if the new value of cr010 is less than the value of 16-bit timer counter 0 (tm00), tm00 continues counting, overflows, and then starts counting from 0 again. if the new value of cr010 is less than the old value , therefore, the timer must be reset to be restarted after the value of cr010 is changed. 3. the value of cr010 after 16-bit timer/ event counter 00 has stopped is not guaranteed. 4. the capture operation may not be perfo rmed for cr010 set in compare mode even if a capture trigger is input. chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 93 cautions 5. if the register read period and the input of the capture trigger conflict when cr010 is used as a capture register, the capture trigge r input takes precedence and the read data is undefined. also, if the timer count stop and the input of the capture trigger conflict, the capture data is undefined. 6. changing the cr010 setting during tm00 operation may cause a malfunction. to change the setting, refer to 6.5 cautions related to 16-bit timer/event counter 00 (17) changing compare register during timer operation. 6.3 registers to control 16-bit timer/event counter 00 the following six types of registers are used to control 16-bit timer/event counter 00. ? 16-bit timer mode control register 00 (tmc00) ? capture/compare control register 00 (crc00) ? 16-bit timer output control register 00 (toc00) ? prescaler mode register 00 (prm00) ? port mode register 3 (pm3) ? port register 3 (p3) (1) 16-bit timer mode control register 00 (tmc00) this register sets the 16-bit timer operating mode, the 16-bit timer count er 00 (tm00) clear mode, and output timing, and detects an overflow. tmc00 is set by a 1-bit or 8-bit memory manipulation instruction. generation of reset signal sets the value of tmc00 to 00h. caution 16-bit timer counter 00 (tm00) starts operation at the moment tmc002 and tmc003 (operation stop mode) are set to a value other than 0, 0, respectively. set tmc002 and tmc003 to 0, 0 to stop the operation. chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 94 figure 6-5. format of 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 3 tmc003 2 tmc002 1 tmc001 <0> ovf00 symbol tmc00 address: ff60h after reset: 00h r/w ovf00 overflow detection of 16-bit timer counter 00 (tm00) 0 overflow not detected 1 overflow detected cautions 1. the timer operation mu st be stopped before writing to bits other than the ovf00 flag. 2. if the timer is stopped, timer counts and ti mer interrupts do not occu r, even if a signal is input to the ti000/ti010 pins. 3. except when the valid edge of the ti000 pin is selected as th e count clock, stop the timer operation before setting stop mode or system clock stop mode; otherwise the timer may malfunction when the system clock starts. 4. set the valid edge of the ti000 pin with bits 4 and 5 of prescaler mode register 00 (prm00) after stopping the timer operation. 5. if the clear & start mode entered on a matc h between tm00 and cr000, clear & start mode at the valid edge of the ti000 pin, or free-running mode is selected, when the set value of cr000 is ffffh and the tm00 value ch anges from ffffh to 0000h, the ovf00 flag is set to 1. 6. even if the ovf00 flag is cleared before the next count clock is counted (before tm00 becomes 0001h) after the occurre nce of a tm00 overflow, the ovf 00 flag is re-set newly and clear is disabled. 7. the capture operation is performed at the fall of the count clock. an interrupt request input (inttm0n0), however, occurs at th e rise of the next count clock. remark tm00: 16-bit timer counter 00 cr000: 16-bit timer capture/compare register 000 cr010: 16-bit timer capture/compare register 010 tmc003 tmc002 tmc001 operating mode and clear mode selection to00 inversion timing selection interrupt request generation 0 0 0 0 0 1 operation stop (tm00 cleared to 0) no change not generated 0 1 0 free-running mode match between tm00 and cr000 or match between tm00 and cr010 0 1 1 match between tm00 and cr000, match between tm00 and cr010 or ti000 pin valid edge 1 0 0 1 0 1 clear & start occurs on valid edge of ti000 pin ? 1 1 0 clear & start occurs on match between tm00 and cr000 match between tm00 and cr000 or match between tm00 and cr010 1 1 1 match between tm00 and cr000, match between tm00 and cr010 or ti000 pin valid edge chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 95 (2) capture/compare control register 00 (crc00) this register controls the op eration of the 16-bit capture/co mpare registers (cr000, cr010). crc00 is set by a 1-bit or 8-bit memory manipulation instruction. generation of reset signal sets the value of crc00 to 00h. figure 6-6. format of capture/co mpare control register 00 (crc00) address: ff62h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 crc00 0 0 0 0 0 crc002 crc001 crc000 crc002 cr010 operating mode selection 0 operate as compare register 1 operate as capture register crc001 cr000 capture trigger selection 0 capture on valid edge of ti010 pin 1 capture on valid edge of ti000 pin by reverse phase note crc000 cr000 operating mode selection 0 operate as compare register 1 operate as capture register note when the crc001 bit value is 1, capture is not performed if both th e rising and falling edges have been selected as the valid edges of the ti000 pin. cautions 1. the timer operation mu st be stopped before setting crc00. 2. when the clear & start mode entered on a match between tm00 and cr000 is selected by 16-bit timer mode control register 00 (t mc00), cr000 should not be specified as a capture register. 3. to ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 00 (prm00) (refer to figure 6-17). chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 96 (3) 16-bit timer output control register 00 (toc00) this register controls the operation of the 16-bit timer/event counter outpu t controller. it sets timer output f/f set/reset, output inversion enable/disable, 16-bit timer/ event counter 00 timer output enable/disable, one-shot pulse output operation enable/disable, and out put trigger of one-shot pulse by software. toc00 is set by a 1-bit or 8-bit memory manipulation instruction. generation of reset signal sets the value of toc00 to 00h. figure 6-7. format of 16-bit timer ou tput control register 00 (toc00) address: ff63h after reset: 00h r/w symbol 7 <6> <5> 4 <3> <2> 1 <0> toc00 0 ospt00 ospe00 toc004 lvs00 lvr00 toc001 toe00 ospt00 one-shot pulse output trigger control via software 0 no one-shot pulse output trigger 1 one-shot pulse output trigger ospe00 one-shot pulse output operation control 0 successive pulse output mode 1 one-shot pulse output mode note toc004 timer output f/f control using match of cr010 and tm00 0 disables inversion operation 1 enables inversion operation lvs00 lvr00 timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited toc001 timer output f/f control using match of cr000 and tm00 0 disables inversion operation 1 enables inversion operation toe00 timer output control 0 disables output (output fixed to level 0) 1 enables output note the one-shot pulse output mode op erates correctly only in the free -running mode and the mode in which clear & start occurs at the ti000 pin valid edge. in the mode in which clear & start occurs on a match between tm00 and cr000, one-shot pul se output is not possible because an overflow does not occur. cautions 1. the timer operation must be stopped before setting other than ospt00. 2. if lvs00 and lvr00 are read, 0 is read. 3. ospt00 is automatically cleared after data is set, so 0 is read. 4. do not set ospt00 to 1 other than in one-shot pulse output mode. 5. a write interval of two cycles or more of th e count clock selected by prescaler mode register 00 (prm00) is required, when o spt00 is set to 1 successively. 6. when toe00 is 0, set to e00, lvs00, and lvr00 at the same time with the 8-bit memory manipulation instruction. when toe00 is 1, lvs00 and lvr00 can be set with the 1-bit memory manipulation instruction. chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 97 (4) prescaler mode register 00 (prm00) this register is used to set the 16-bit timer counter 00 (tm00) count clock and the ti000, ti010 pin input valid edges. prm00 is set by a 1-bit or 8-bit memory manipulation instruction. generation of reset signal sets the value of prm00 to 00h. figure 6-8. format of prescaler mode register 00 (prm00) address: ff61h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 prm00 es110 es100 es010 es000 0 0 prm001 prm000 es110 es100 ti010 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es010 es000 ti000 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges prm001 prm000 count clock selection 0 0 f xp (10 mhz) 0 1 f xp /2 2 (2.5 mhz) 1 0 f xp /2 8 (39.06 khz) 1 1 ti000 pin valid edge note remarks 1. f xp : oscillation frequency of clock supplied to peripheral hardware 2. ( ): f xp = 10 mhz note the external clock requires a pulse longer than two cycles of the internal count clock (f xp ). chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 98 cautions 1. always set data to prm 00 after stopping the timer operation. 2. if the valid edge of the ti000 pin is to be set as the count clock, do not set the clear/start mode and the capture trigger at th e valid edge of the ti000 pin. 3. in the following cases, note with caution that the valid edge of the ti0n0 pin is detected. <1> immediately after a system reset, if a high level is input to the ti0n0 pin, the operation of the 16-bit timer counter 00 (tm00) is enabled if the rising edge or both rising and fal ling edges are specified as the valid edge of the ti0n0 pin, a rising edge is detect ed immediately after the tm00 operation is enabled. <2> if the tm00 operation is stopped while the ti0n0 pin is high level, tm00 operation is then enabled after a low level is input to the ti0n0 pin if the falling edge or both rising and fa lling edges are specifi ed as the valid edge of the ti0n0 pin, a falling edge is detect ed immediately after the tm00 operation is enabled. <3> if the tm00 operation is stopped while the ti0n0 pin is low level, tm00 operation is then enabled after a high level is input to the ti0n0 pin if the rising edge or both rising and fal ling edges are specified as the valid edge of the ti0n0 pin, a rising edge is detect ed immediately after the tm00 operation is enabled. 4. the sampling clock used to eliminate noise differs when a ti000 valid edge is used as the count clock and when it is used as a capture trigger. in the former case, the count clock is f xp , and in the latter case the count clock is selected by prescaler mode register 00 (prm00). the capture operation is not performe d until the valid edge is sampled and the valid level is detected twice, thus eliminating noise with a short pulse width. 5. when using p31 as the input pin (ti010) of the valid edge, it cannot be used as a timer output pin (to00). when using p31 as the time r output pin (to00), it cannot be used as the input pin (ti010) of the valid edge. remark n = 0, 1 (5) port mode register 3 (pm3) this register sets port 3 input/output in 1-bit units. when using the p31/to00/ti010/intp2 pin for timer out put, set pm31 and the output latch of p31 to 0. when using the p30/ti000/intp0 and p31/to00/ti010/intp2 pins as a timer input, set pm30 and pm31 to 1. at this time, the output latches of p30 and p31 can be either 0 or 1. pm3 is set by a 1-bit or 8-bit memory manipulation instruction. generation of reset signal sets the value of pm3 to ffh. figure 6-9. format of port mode register 3 (pm3) 7 1 6 1 5 1 4 1 3 pm33 2 pm32 1 pm31 0 pm30 symbol pm3 address: ff23h after reset: ffh r/w pm3n 0 1 p3n pin i/o mode selection (n = 0 to 3) output mode (output buffer on) input mode (output buffer off) chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 99 6.4 operation of 16-bit timer/event counter 00 6.4.1 interval timer operation setting 16-bit timer mode control register 00 (tmc00) and capture/compare control register 00 (crc00) as shown in figure 6-10 allows operation as an interval timer. setting the basic operation setting procedure is as follows. <1> set the crc00 register (see figure 6-10 for the set value). <2> set any value to the cr000 register. <3> set the count clock by using the prm00 register. <4> set the tmc00 register to start the operation (see figure 6-10 for the set value). caution changing the cr000 setti ng during tm00 operation may cause a malfunction. to change the setting, refer to 6.5 cautions related to 16-bi t timer/event counter 00 (17) changing compare register during timer operation. remark for how to enable the inttm000 interrupt, see chapter 13 interrupt functions . interrupt requests are generated repeatedly using the count value set in 16-bit timer capture/compare register 000 (cr000) beforehand as the interval. when the count value of 16-bit timer counter 00 (tm00) matches the value set to cr 000, counting continues with the tm00 value cleared to 0 and the interrupt request signal (inttm000) is generated. the count clock of the 16-bit timer/ev ent counter can be selected using bits 0 and 1 (prm000, prm001) of prescaler mode register 00 (prm00). chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 100 figure 6-10. control register setti ngs for interval timer operation (a) capture/compare control register 00 (crc00) 7 0 6 0 5 0 4 0 3 0 crc002 0/1 crc001 0/1 crc000 0 crc00 cr000 used as compare register (b) prescaler mode register 00 (prm00) es110 0/1 es100 0/1 es010 0/1 es000 0/1 3 0 2 0 prm001 0/1 prm000 0/1 prm00 selects count clock. setting invalid (setting ?10? is prohibited.) setting invalid (setting ?10? is prohibited.) (c) 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 tmc003 1 tmc002 1 tmc001 0/1 ovf00 0 tmc00 clears and starts on match between tm00 and cr000. remark 0/1: setting 0 or 1 allows another function to be us ed simultaneously with the interval timer. see the description of the respective control registers for details. figure 6-11. interval ti mer configuration diagram 16-bit timer capture/compare register 000 (cr000) 16-bit timer counter 00 (tm00) ovf00 clear circuit inttm000 f xp f xp /2 2 f xp /2 8 ti000/intp0/p30 selector noise eliminator f xp note note ovf00 is set to 1 only when 16-bit timer captur e/compare register 000 (cr000) is set to ffffh. chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 101 figure 6-12. timing of interval timer operation count clock t tm00 count value cr000 inttm000 0000h 0001h n 0000h 0001h n 0000h 0001h n n n n n timer operation enabled clear clear interrupt request generated interrupt request generated remark interval time = (n + 1) t n = 0001h to ffffh (settable range) when the compare register is changed dur ing timer count operation, if the val ue after 16-bit timer capture/compare register 000 (cr000) is changed is smaller than that of 16-bit timer count er 00 (tm00), tm00 continues counting, overflows and then restarts counting from 0. thus, if the value (m) after the cr000 change is smaller than that (n) before the change, it is necessary to restart the timer after changing cr000. figure 6-13. timing after change of compar e register during timer count operation (n m: n > m) cr000 nm count clock tm00 count value x ? 1 x ffffh 0000h 0001h 0002h remark n > x > m 6.4.2 external event counter operation setting the basic operation setting procedure is as follows. <1> set the crc00 register (see figure 6-14 for the set value). <2> set the count clock by using the prm00 register. <3> set any value to the cr000 register (0000h cannot be set). <4> set the tmc00 register to start the operation (see figure 6-14 for the set value). remarks 1. for the setting of the ti000 pin, see 6.3 (5) port mode register 3 (pm3) . 2. for how to enable the inttm000 interrupt, see chapter 13 interrupt functions . chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 102 the external event counter c ounts the number of external clock pulses to be input to the ti000 pin with using 16-bit timer counter 00 (tm00). tm00 is incremented each time the valid edge specified by prescaler mode register 00 (prm00) is input. when the tm00 count value matches the 16-bit timer capt ure/compare register 000 (cr000) value, tm00 is cleared to 0 and the interrupt requ est signal (inttm000) is generated. input a value other than 0000h to cr000. (a c ount operation with a pulse cannot be carried out.) the rising edge, the falling edge, or both edges can be selected using bits 4 and 5 (es000 and es010) of prescaler mode register 00 (prm00). because an operation is carried out only when the valid ed ge of the ti000 pin is detec ted twice after sampling with the internal clock (f xp ), noise with a short pulse width can be removed. figure 6-14. control register setti ngs in external event counter mode (with rising edge specified) (a) capture/compare control register 00 (crc00) 7 0 6 0 5 0 4 0 3 0 crc002 0/1 crc001 0/1 crc000 0 crc00 cr000 used as compare register (b) prescaler mode register 00 (prm00) es110 0/1 es100 0/1 es010 0 es000 1 3 0 2 0 prm001 1 prm000 1 prm00 selects external clock. specifies rising edge for pulse width detection. setting invalid (setting ?10? is prohibited.) (c) 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 tmc003 1 tmc002 1 tmc001 0/1 ovf00 0 tmc00 clears and starts on match between tm00 and cr000. remark 0/1: setting 0 or 1 allows another function to be used simultaneously with the external event counter. see the description of the respecti ve control registers for details. chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 103 figure 6-15. external event counter configuration diagram 16-bit timer capture/compare register 000 (cr000) 16-bit timer counter 00 (tm00) internal bus match clear ovf00 note inttm000 noise eliminator f xp valid edge of ti000 note ovf00 is 1 only when 16-bit timer capture/co mpare register 000 (cr000) is set to ffffh. figure 6-16. external event counter oper ation timing (with rising edge specified) (1) inttm000 generation timing imme diately after operation starts counting is started after a va lid edge is detected twice. cr000 inttm000 0000h 0001h 0002h 0003h n-2 n-1 n 0000h 0001h 0002h n 1 23 count starts timer operation starts ti000 pin input tm00 count value (2) inttm000 generation ti ming after inttm000 has been generated twice cr000 inttm000 n 0000h 0001h 0002h 0003h 0004h n-1 n 0000h 0001h 0002h 0003h n ti000 pin input tm00 count value caution when reading the ext ernal event counter count value, tm00 should be read. chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 104 6.4.3 pulse width measurement operations it is possible to measure the pulse width of the signal s input to the ti000 pin and ti010 pin using 16-bit timer counter 00 (tm00). there are two measurement methods : measuring with tm00 used in free -running mode, and measuring by restarting the timer in synchronization with th e edge of the signal in put to the ti000 pin. when an interrupt occurs, read the valid value of the capt ure register, check the overflow flag, and then calculate the necessary pulse width. clear the overflow flag after checking it. the capture operation is not performed unt il the signal pulse width is sampl ed in the count clock cycle selected by prescaler mode register 00 (prm00) and the valid level of the ti000 or ti010 pin is dete cted twice, thus eliminating noise with a short pulse width. figure 6-17. cr010 capture operat ion with rising edge specified count clock tm00 ti000 rising edge detection cr010 inttm010 n ? 3n ? 2n ? 1 n n + 1 n setting the basic operation setting procedure is as follows. <1> set the crc00 register (see figures 6-18 , 6-21 , 6-23 , and 6-25 for the set value). <2> set the count clock by using the prm00 register. <3> set the tmc00 register to start the operation (see figures 6-18 , 6-21 , 6-23 , and 6-25 for the set value). caution to use two capture regist ers, set the ti000 and ti010 pins. remarks 1. for the setting of the ti000 (or ti010) pin, see 6.3 (5) port mode register 3 (pm3) . 2. for how to enable the inttm000 (or inttm010) interrupt, see chapter 13 interrupt functions . chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 105 (1) pulse width measurement with free-runni ng counter and one capture register specify both the rising and falling edges as the valid edg es of the ti000 pin, by us ing bits 4 and 5 (es000 and es010) of prm00. when 16-bit timer counter 00 (tm00) is operated in free-running mode, and the valid edge specified by prm00 is input, the value of tm00 is taken into 16-b it timer capture/compare register 010 (cr010) and an external interrupt request signal (inttm010) is set. sampling is performed using the count clock selected by prm00, and a capture operation is only performed when a valid level of the ti000 pin is detected twic e, thus eliminating noise with a short pulse width. caution the measurable pulse width in this operat ion example is up to 1 cycle of the timer counter. figure 6-18. control register settings for pul se width measurement with free-running counter and one capture register (when ti000 and cr010 are used) (a) capture/compare control register 00 (crc00) 7 0 6 0 5 0 4 0 3 0 crc002 1 crc001 0/1 crc000 0 crc00 cr000 used as compare register cr010 used as capture register (b) prescaler mode register 00 (prm00) es101 0/1 es100 0/1 es010 1 es000 1 3 0 2 0 prm001 0/1 prm000 0/1 prm00 selects count clock (setting ?11? is prohibited). specifies both edges for pulse width detection. setting invalid (setting ?10? is prohibited.) (c) 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 tmc003 0 tmc002 1 tmc001 0/1 ovf00 0 tmc00 free-running mode remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respecti ve control registers for details. chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 106 figure 6-19. configuration di agram for pulse width measure ment by free-running counter f xp f xp /2 2 f xp /2 6 ti000/intp0/p30 16-bit timer/counter 00 (tm00) 16-bit timer capture/compare register 010 (cr010) internal bus inttm010 selector figure 6-20. timing of pulse width measure ment operation by free-running counter and one capture register (with both edges specified) t 0000h 0000h ffffh 0001h d0 d0 (d1 ? d0) t (d3 ? d2) t (d2 ? d1) t d1 d2 d3 d2 d3 d0 + 1 d1 d1 + 1 note count clock tm00 count value ti000 pin input cr010 capture value inttm010 note the carry flag is set to 1. ignore this setting. chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 107 (2) measurement of two pulse widths with free-running counter when 16-bit timer counter 00 (tm00) is operated in fr ee-running mode, it is possible to simultaneously measure the pulse widths of the two signal s input to the ti000 pin and the ti010 pin. specify both the rising and falling ed ges as the valid edges of the ti000 and ti010 pins, by using bits 4 and 5 (es000 and es010) and bits 6 and 7 (es100 and es110) of prm00. when the valid edge specified by bits 4 and 5 (es000 and es010) of prm00 is in put to the ti000 pin, the value of tm00 is taken into 16-bit timer capture/co mpare register 000 (cr010) and an interrupt request signal (inttm010) is set. also, when the valid edge specified by bits 6 and 7 (e s100 and es110) of prm00 is input to the ti010 pin, the value of tm00 is taken into 16-bit timer capture/co mpare register 000 (cr000) and an interrupt request signal (inttm000) is set. sampling is performed using the count clock cycle sele cted by prescaler mode register 00 (prm00), and a capture operation is only performed when a valid leve l of the ti000 or ti010 pin is detected twice, thus eliminating noise with a short pulse width. caution the measurable pulse width in this operat ion example is up to 1 cycle of the timer counter. figure 6-21. control register settings for measure ment of two pulse widths with free-running counter (a) capture/compare control register 00 (crc00) 7 0 6 0 5 0 4 0 3 0 crc002 1 crc001 0 crc000 1 crc00 cr000 used as capture register captures valid edge of ti010 pin to cr000. cr010 used as capture register (b) prescaler mode register 00 (prm00) es110 1 es100 1 es010 1 es000 1 3 0 2 0 prm001 0/1 prm000 0/1 prm00 selects count clock (setting ?11? is prohibited). specifies both edges for pulse width detection. specifies both edges for pulse width detection. (c) 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 tmc003 0 tmc002 1 tmc001 0/1 ovf00 0 tmc00 free-running mode remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respecti ve control registers for details. chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 108 figure 6-22. timing of pulse width measureme nt operation with free-running counter (with both edges specified) t 0000h 0000h ffffh 0001h d0 d0 (d1 ? d0) t (d3 ? d2) t (d2 ? d1) t ((d2 + 1) ? d1) t d1 d2 + 1 d1 d2 d2 d3 d0 + 1 d1 d1 + 1 d2 + 1 d2 + 2 note ti010 pin input cr000 capture value inttm010 inttm000 count clock tm00 count value ti000 pin input cr010 capture value note note the carry flag is set to 1. ignore this setting. (3) pulse width measurement with free-runni ng counter and two capture registers when 16-bit timer counter 00 (tm00) is operated in free-running mode, it is possible to measure the pulse width of the signal input to the ti000 pin. when the rising or falling edge specified by bits 4 an d 5 (es000 and es010) of prescaler mode register 00 (prm00) is input to the ti000 pin, the value of tm00 is taken into 16-bit timer capture/compare register 010 (cr010) and an interrupt request signal (inttm010) is set. also, when the inverse edge to that of the capture operation is input into cr010, the value of tm00 is taken into 16-bit timer capture/compare register 000 (cr000). sampling is performed using the count clock cycle sele cted by prescaler mode register 00 (prm00), and a capture operation is only performed when a valid level of the ti000 pin is detected twice, thus eliminating noise with a short pulse width. caution the measurable pulse width in this operat ion example is up to 1 cycle of the timer counter. chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 109 figure 6-23. control register settings for pulse width measurement with fr ee-running counter and two capture registers (with rising edge specified) (a) capture/compare control register 00 (crc00) 7 0 6 0 5 0 4 0 3 0 crc002 1 crc001 1 crc000 1 crc00 cr000 used as capture register captures to cr000 at inverse edge to valid edge of ti000 note . cr010 used as capture register (b) prescaler mode register 00 (prm00) es110 0/1 es100 0/1 es010 0 es000 1 3 0 2 0 prm001 0/1 prm000 0/1 prm00 selects count clock (setting ?11? is prohibited). specifies rising edge for pulse width detection. setting invalid (setting ?10? is prohibited.) (c) 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 tmc003 0 tmc002 1 tmc001 0/1 ovf00 0 tmc00 free-running mode note if the valid edge of the ti000 pin is specified to be both the rising and falling edges, 16-bit timer capture/compare register 000 (cr000) cannot perform t he capture operation. when the crc001 bit value is 1, the tm00 count value is not c aptured in the cr000 register when a valid edge of the ti010 pin is detected, but the input from the ti010 pin can be used as an external interrupt source because inttm000 is generated at that timing. remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respecti ve control registers for details. chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 110 figure 6-24. timing of pulse width measure ment operation by free-running counter and two capture registers (with rising edge specified) t 0000h 0000h ffffh 0001h d0 d0 d2 d1 d3 d2 d3 d1 d0 + 1 d2 + 1 d1 + 1 inttm010 cr000 capture value count clock tm00 count value ti000 pin input cr010 capture value (d1 ? d0) t (d3 ? d2) t (d2 ? d1) t note note the carry flag is set to 1. ignore this setting. (4) pulse width measurement by means of restart specify both the rising and falling edges as the valid edg es of the ti000 pin, by us ing bits 4 and 5 (es000 and es010) of prm00. when a valid edge of the ti000 pin is det ected, the count value of 16-bit time r/counter 00 (tm00) is taken into 16-bit timer capture/compare register 010 (cr010), and then the pulse width of the si gnal input to the ti000 pin is measured by clearing tm00 and restarting the count. sampling is performed at the interval selected by pr escaler mode register 00 (prm 00) and a capture operation is only performed when a valid level of the ti000 pin is detected twice, thus elim inating noise with a short pulse width. caution the measurable pulse width in this operat ion example is up to 1 cycle of the timer counter. chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 111 figure 6-25. control register settings for pu lse width measurement by means of restart (with rising edge specified) (a) capture/compare control register 00 (crc00) 7 0 6 0 5 0 4 0 3 0 crc002 1 crc001 1 crc000 1 crc00 cr000 used as capture register captures to cr000 at inverse edge to valid edge of ti000 note . cr010 used as capture register (b) prescaler mode register 00 (prm00) es110 0/1 es100 0/1 es010 0 es000 1 3 0 2 0 prm001 0/1 prm000 0/1 prm00 selects count clock (setting ?11? is prohibited). specifies rising edge for pulse width detection. setting invalid (setting ?10? is prohibited.) (c) 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 tmc003 1 tmc002 0 tmc001 0/1 ovf00 0 tmc00 clears and starts at valid edge of ti000 pin. note if the valid edge of the ti000 pin is specified to be both the rising and falling edges, 16-bit timer capture/compare register 000 (cr000) cannot perform the capture operation. figure 6-26. timing of pulse width measure ment operation by means of restart (with rising edge specified) t 0000h 0001h 0000h 0001h 0000h 0001h d0 d0 inttm010 (d1 + 1) t (d2 + 1) t d2 d1 d2 d1 cr000 capture value count clock tm00 count value ti000 pin input cr010 capture value chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 112 6.4.4 square-wave output operation setting the basic operation setting procedure is as follows. <1> set the count clock by using the prm00 register. <2> set the crc00 register (see figure 6-27 for the set value). <3> set the toc00 register (see figure 6-27 for the set value). <4> set any value to the cr000 register (0000h cannot be set). <5> set the tmc00 register to start the operation (see figure 6-27 for the set value). caution changing the cr000 setti ng during tm00 operation may cause a malfunction. to change the setting, refer to 6.5 cautions related to 16-bi t timer/event counter 00 (17) changing compare register during timer operation. remarks 1. for the setting of the to00 pin, see 6.3 (5) port mode register 3 (pm3) . 2. for how to enable the inttm000 interrupt, see chapter 13 interrupt functions . a square wave with any selected frequency can be output at intervals determined by the count value preset to 16- bit timer capture/compare register 000 (cr000). the to00 pin output status is reversed at intervals determined by the count value preset to cr000 + 1 by setting bit 0 (toe00) and bit 1 (toc001) of 16-bit timer output control register 00 (toc00) to 1. this enables a square wave with any selected frequency to be output. figure 6-27. control register settings in square-wave output mode (1/2) (a) prescaler mode register 00 (prm00) es110 0/1 es100 0/1 es010 0/1 es000 0/1 3 0 2 0 prm001 0/1 prm000 0/1 prm00 selects count clock. setting invalid (setting ?10? is prohibited.) setting invalid (setting ?10? is prohibited.) (b) capture/compare cont rol register 00 (crc00) 7 0 6 0 5 0 4 0 3 0 crc002 0/1 crc001 0/1 crc000 0 crc00 cr000 used as compare register chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 113 figure 6-27. control register settings in square-wave output mode (2/2) (c) 16-bit timer output control register 00 (toc00) 7 0 ospt00 0 ospe00 0 toc004 0 lvs00 0/1 lvr00 0/1 toc001 1 toe00 1 toc00 enables to00 output. inverts output on match between tm00 and cr000. specifies initial value of to00 output f/f (setting ?11? is prohibited). does not invert output on match between tm00 and cr010. disables one-shot pulse output. (d) 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 tmc003 1 tmc002 1 tmc001 0 ovf00 0 tmc00 clears and starts on match between tm00 and cr000. remark 0/1: setting 0 or 1 allows another function to be used simultaneously with square-wave output. see the description of the respective control registers for details. figure 6-28. square-wave output operation timing count clock tm00 count value cr000 inttm000 to00 pin output 0000h 0001h 0002h n ? 1n 0000h 0001h 0002h n ? 1n 0000h n chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 114 6.4.5 ppg output operations setting 16-bit timer mode control register 00 (tmc00) and capture/compare control register 00 (crc00) as shown in figure 6-29 allows operation as ppg (programmable pulse generator) output. setting the basic operation setting procedure is as follows. <1> set the crc00 register (see figure 6-29 for the set value). <2> set any value to the cr000 register as the cycle. <3> set any value to the cr010 register as the duty factor. <4> set the toc00 register (see figure 6-29 for the set value). <5> set the count clock by using the prm00 register. <6> set the tmc00 register to start the operation (see figure 6-29 for the set value). caution changing the crc0n0 setti ng during tm00 operation may cause a malfunction. to change the setting, refer to 6.5 cautions related to 16-bi t timer/event counter 00 (17) changing compare register during timer operation. remarks 1. for the setting of the to00 pin, see 6.3 (5) port mode register 3 (pm3) . 2. for how to enable the inttm000 interrupt, see chapter 13 interrupt functions . 3. n = 0 or 1 in the ppg output oper ation, rectangular wa ves are output from the to00 pin with the pulse wi dth and the cycle that correspond to the count values preset in 16-bit time r capture/compare register 010 (cr010) and in 16-bit timer capture/compare register 000 (cr000), respectively. chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 115 figure 6-29. control register settings for ppg output operation (a) capture/compare control register 00 (crc00) 7 0 6 0 5 0 4 0 3 0 crc002 0 crc001 crc000 0 crc00 cr000 used as compare register cr010 used as compare register (b) 16-bit timer output control register 00 (toc00) 7 0 ospt00 0 ospe00 0 toc004 1 lvs00 0/1 lvr00 0/1 toc001 1 toe00 1 toc00 enables to00 output. inverts output on match between tm00 and cr000. specifies initial value of to00 output f/f (setting "11" is prohibited). inverts output on match between tm00 and cr010. disables one-shot pulse output. (c) prescaler mode register 00 (prm00) es110 0/1 es100 0/1 es010 0/1 es000 0/1 3 0 2 0 prm001 0/1 prm000 0/1 prm00 selects count clock. setting invalid (setting ?10? is prohibited.) setting invalid (setting ?10? is prohibited.) (d) 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 tmc003 1 tmc002 1 tmc001 0 ovf00 0 tmc00 clears and starts on match between tm00 and cr000. cautions 1. values in the following ra nge should be set in cr000 and cr010. 0000h < cr010 < cr000 ffffh 2. the cycle of the pulse generated through ppg output (cr000 setting value + 1) has a duty of (cr010 setting value + 1)/(cr000 setting value + 1). remark : don?t care chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 116 figure 6-30. configuration diagram of ppg output 16-bit timer capture/compare register 000 (cr000) 16-bit timer counter 00 (tm00) clear circuit noise eliminator f xp f xp f xp /2 2 f xp /2 8 ti000/intp0/p30 16-bit timer capture/compare register 010 (cr010) to00/ti010/ intp2/p31 selector output controller figure 6-31. ppg output operation timing t 0000h 0000h 0001h 0001h m ? 1 count clock tm00 count value to00 pulse width: (m + 1) t 1 cycle: (n + 1) t n cr000 capture value cr010 capture value m m n ? 1 n n clear clear remark 0000h < m < n ffffh chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 117 6.4.6 one-shot pulse output operation 16-bit timer/event counter 00 can output a one-shot pulse in synchronization with a software trigger or an external trigger (ti000 pin input). setting the basic operation setting procedure is as follows. <1> set the count clock by using the prm00 register. <2> set the crc00 register (see figures 6-32 and 6-34 for the set value). <3> set the toc00 register (see figures 6-32 and 6-34 for the set value). <4> set any value to the cr000 and cr010 registers (0000h cannot be set). <5> set the tmc00 register to start the operation (see figures 6-32 and 6-34 for the set value). remarks 1. for the setting of the to00 pin, see 6.3 (5) port mode register 3 (pm3) . 2. for how to enable the inttm000 (if necessary, inttm010) interrupt, see chapter 13 interrupt functions . (1) one-shot pulse output with software trigger a one-shot pulse can be output from the to00 pin by setting 16-bit timer mode control register 00 (tmc00), capture/compare control register 00 (crc00), and 16-bit ti mer output control register 00 (toc00) as shown in figure 6-32, and by setting bit 6 (ospt00) of the toc00 register to 1 by software. by setting the ospt00 bit to 1, 16-bit timer/event count er 00 is cleared and start ed, and its output becomes active at the count value (n) set in advance to 16-bit ti mer capture/compare register 010 (cr010). after that, the output becomes inactive at the count value (m) set in advance to 16-bit timer capture/compare register 000 (cr000) note . even after the one-shot pulse has been output, the tm00 r egister continues its operat ion. to stop the tm00 register, the tmc003 and tmc002 bits of the tmc00 register must be cleared to 00. note the case where n < m is described here. w hen n > m, the output becom es active with the cr000 register and inactive with the cr010 register. do not set n to m. cautions 1. do not set the ospt00 bit to 1 again while the one-shot pulse is being output. to output the one-shot pulse again, wait until the current one-shot pulse output is completed. 2. when using the one-shot pulse output of 16-bit timer/event counter 00 with a software trigger, do not change the level of the ti000 pin or its alternate-function port pin. because the external trigger is valid even in this case, the ti mer is cleared and started even at the level of the ti000 pin or its alternate-function port pin, resulting in the output of a pulse at an undesired timing. chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 118 figure 6-32. control register settings for on e-shot pulse output with software trigger (a) prescaler mode register 00 (prm00) 0/1 0/1 0/1 0/1 0 prm00 prm001 prm000 selects count clock. setting invalid (setting ?10? is prohibited.) 0 0/1 0/1 es110 es100 es010 es000 setting invalid (setting ?10? is prohibited.) 32 (b) capture/compare control register 00 (crc00) 00000 76543 crc00 crc002 crc001 crc000 cr000 as compare register cr010 as compare register 0 0/1 0 (c) 16-bit timer output control register 00 (toc00) 0 7 0 1 1 0/1 toc00 lvr00 lvs00 toc004 ospe00 ospt00 toc001 toe00 enables to00 output. inverts output upon match between tm00 and cr000. specifies initial value of to00 output f/f (setting ?11? is prohibited.) inverts output upon match between tm00 and cr010. sets one-shot pulse output mode. set to 1 for output. 0/1 1 1 (d) 16-bit timer mode control register 00 (tmc00) 0000 7654 0 tmc003 tmc00 tmc002 tmc001 ovf00 free-running mode 100 caution do not set 0000h to th e cr000 and cr010 registers. chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 119 figure 6-33. timing of one-shot pulse output operation with software trigger 0000h n nn n n mm m m nm n + 1 n ? 1m ? 1 0001h m + 1 m + 2 0000h count clock tm00 count cr010 set value cr000 set value ospt00 inttm010 inttm000 to00 pin output set tmc00 to 04h (tm00 count starts) caution 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop mode) is set to the tmc003 and tmc002 bits. remark n < m (2) one-shot pulse output with external trigger a one-shot pulse can be output from the to00 pin by setting 16-bit timer mode control register 00 (tmc00), capture/compare control register 00 (crc00), and 16-bit ti mer output control register 00 (toc00) as shown in figure 6-34, and by using the valid edge of the ti000 pin as an external trigger. the valid edge of the ti000 pin is specified by bits 4 and 5 (es000, es 010) of prescaler mode register 00 (prm00). the rising, falling, or both the rising and falling edges can be specified. when the valid edge of the ti000 pin is detected, the 16-bit timer/event count er is cleared and started, and the output becomes active at the count value set in adv ance to 16-bit timer capture/compare register 010 (cr010). after that, the output becomes inactive at the count value set in advance to 16-bit timer capture/compare register 000 (cr000) note . note the case where n < m is described here. when n > m, the output becomes active with the cr000 register and inactive with the cr010 register. do not set n to m. caution do not input the external trigger again wh ile the one-shot pulse is being output. to output the one-shot pulse again, wait until the curre nt one-shot pulse output is completed. chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 120 figure 6-34. control register settings for on e-shot pulse output with external trigger (with rising edge specified) (a) prescaler mode register 00 (prm00) 0/1 0/1 0 1 prm00 prm001 prm000 selects count clock (setting ?11? is prohibited). specifies the rising edge for pulse width detection. 0/1 0/1 es110 es100 es010 es000 setting invalid (setting ?10? is prohibited.) 00 32 (b) capture/compare cont rol register 00 (crc00) 00000 76543 crc00 crc002 crc001 crc000 cr000 used as compare register cr010 used as compare register 0 0/1 0 (c) 16-bit timer output control register 00 (toc00) 0 7 01 1 0/1 toc00 lvr00 toc001 toe00 ospe00 ospt00 toc004 lvs00 enables to00 output. inverts output upon match between tm00 and cr000. specifies initial value of to00 output f/f (setting ?11? is prohibited.) inverts output upon match between tm00 and cr010. sets one-shot pulse output mode. 0/1 1 1 (d) 16-bit timer mode control register 00 (tmc00) 0000 7654 1 tmc003 tmc00 tmc002 tmc001 ovf00 clears and starts at valid edge of ti000 pin. 000 caution do not set 0000h to th e cr000 and cr010 registers. chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 121 figure 6-35. timing of one-shot pulse output operation with external trigger (wit h rising edge specified) 0000h n nn n n mm m m m n + 1 n + 2 m + 1 m + 2 m ? 2m ? 1 0001h 0000h count clock tm00 count value cr010 set value cr000 set value ti000 pin input inttm010 inttm000 to00 pin output when tmc00 is set to 08h (tm00 count starts) t caution 16-bit timer counter 00 starts operating as soon as a value other than 0, 0 (operation stop mode) is set to the tmc003 and tmc002 bits. remark n < m chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 122 6.5 cautions related to 16-bit timer/event counter 00 (1) timer start errors an error of up to one clock may occur in the time requir ed for a match signal to be generated after timer start. this is because 16-bit timer counter 00 (tm00) is started asynchronously to the count clock. figure 6-36. start timing of 16-bit timer counter 00 (tm00) tm00 count value 0000h 0001h 0002h 0004h count clock timer start 0003h (2) 16-bit timer counter 00 (tm00) operation <1> 16-bit timer counter 00 (tm00) starts operati on at the moment tmc002 and tmc003 (operation stop mode) are set to a value other than 0, 0, respecti vely. set tmc002 and tmc003 to 0, 0 to stop the operation. <2> even if tm00 is read, the value is not captured by 16-bit timer capture/compare register 010 (cr010). <3> when tm00 is read, count misses do not occur, since the input of the count clock is temporarily stopped and then resumed after the read. <4> if the timer is stopped, timer counts and timer inte rrupts do not occur, even if a signal is input to the ti000/ti010 pins. (3) setting of 16-bit timer capture/compare registers 000, 010 (cr000, cr010) <1> set 16-bit timer capture/compare register 000 (cr0 00) to other than 0000h in the clear & start mode entered on match between tm00 and cr000. this m eans a 1-pulse count operation cannot be performed when this register is used as an external event counter. <2> when the clear & start mode entered on a matc h between tm00 and cr000 is selected, cr000 should not be specified as a capture register. <3> in the free-running mode and in the clear & start m ode using the valid edge of t he ti000 pin, if cr0n0 is set to 0000h, an interrupt request (inttm0n0) is generated when cr0n0 changes from 0000h to 0001h following overflow (ffffh). <4> if the new value of cr0n0 is less than the value of tm00, tm00 continues c ounting, overflows, and then starts counting from 0 again. if the new value of cr0n0 is less than the old value, therefore, the timer must be reset to be restarted after the value of cr0n0 is changed. chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 123 (4) capture register data retention the value of 16-bit timer capture/compare register 0n0 (cr0n0) after 16-bit timer/event counter 00 has stopped is not guaranteed. remark n = 0, 1 (5) setting of 16-bit timer mode control register 00 (tmc00) the timer operation must be stopped before writ ing to bits other than the ovf00 flag. (6) setting of capture/compare control register 00 (crc00) the timer operation must be stopped before setting crc00. (7) setting of 16-bit timer output control register 00 (toc00) <1> timer operation must be stopped be fore setting other than ospt00. <2> if lvs00 and lvr00 are read, 0 is read. <3> ospt00 is automatically cleared after data is set, so 0 is read. <4> do not set ospt00 to 1 other t han in one-shot pulse output mode. <5> a write interval of two cycles or more of the c ount clock selected by prescaler mode register 00 (prm00) is required, when ospt00 is set to 1 successively. (8) setting of prescaler mode register 00 (prm00) always set data to prm00 after stopping the timer operation. (9) valid edge setting set the valid edge of the ti000 pin with bits 4 and 5 (es000 and es010) of prescaler mode register 00 (prm00) after stopping the timer operation. (10) one-shot pulse output one-shot pulse output normally operates only in the free-running mode or in the clear & start mode at the valid edge of the ti000 pin. because an overflow does not occur in the clear & start mode on a match between tm00 and cr000, one-shot pulse output is not possible. (11) one-shot pulse output by software <1> do not set the ospt00 bit to 1 again while the one- shot pulse is being outpu t. to output the one-shot pulse again, wait until the current one- shot pulse output is completed. <2> when using the one-shot pulse out put of 16-bit timer/event counter 00 with a software trigger, do not change the level of the ti000 pin or its alternate functi on port pin. because the external trigger is valid even in this case, the timer is cleared and started even at the level of the ti 000 pin or its alternate function port pin, resulting in the out put of a pulse at an undesired timing. <3> do not set the 16-bit timer capture/compare registers 000 and 010 (cr000 and cr010) to 0000h. chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 124 (12) one-shot pulse out put with external trigger <1> do not input the external trigger again while the on e-shot pulse is being output. to output the one-shot pulse again, wait until the current one- shot pulse output is completed. <2> do not set the 16-bit timer capture/compare registers 000 and 010 (cr000 and cr010) to 0000h. (13) operation of ovf00 flag <1> the ovf00 flag is also set to 1 in the following case. either of the clear & start m ode entered on a match between tm00 and cr0 00, clear & start at the valid edge of the ti000 pin, or fr ee-running mode is selected. cr000 is set to ffffh. when tm00 is counted up from ffffh to 0000h. figure 6-37. operation timing of ovf00 flag count clock cr000 tm00 ovf00 inttm000 ffffh fffeh ffffh 0000h 0001h <2> even if the ovf00 flag is clear ed before the next count clock is counted (before tm00 becomes 0001h) after the occurrence of a tm00 overflow, the ovf 00 flag is re-set newly and clear is disabled. chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 125 (14) conflicting operations if the register read period and the i nput of the capture trigger conflict w hen cr000/cr010 is used as a capture register, the capture trigger input ta kes precedence and the read data is und efined. also, if the count stop of the timer and the input of the capture trigger conflict, the captured data is undefined. figure 6-38. capture regist er data retention timing n n + 1 n + 2 m m + 1 m + 2 x n + 2 m + 1 count clock tm00 count value edge input inttm010 capture read signal cr010 capture value capture, but read value is not guaranteed capture (15) capture operation <1> if the valid edge of the ti000 pin is to be set as the count clock, do not set the clear/start mode and the capture trigger at the valid edge of the ti000 pin. <2> if both the rising and falling edges are selected as the valid edges of the ti000 pin, capture is not performed. <3> when the crc001 bit value is 1, the tm00 count va lue is not captured in t he cr000 register when a valid edge of the ti010 pin is detec ted, but the input from the ti 010 pin can be used as an external interrupt source because inttm000 is generated at that timing. <4> to ensure the reliability of the capture operation, the c apture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 00 (prm00). <5> the capture operation is performed at the fall of the count clock. an interrupt request input (inttm0n0), however, occurs at the rise of the next count clock. <6> to use two capture register s, set the ti000 and ti010 pins. remark n = 0, 1 chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 126 (16) compare operation the capture operation may not be performed for cr0n0 set in compare mode even if a capture trigger is input. remark n = 0, 1 (17) changing compare regi ster during timer operation <1> with the 16-bit timer capture/compare register 0n0 (cr0n0) used as a compare register, when changing cr0n0 around the timing of a match between 16-bit timer counter 00 (tm00) and 16-bit timer capture/compare register 0n0 (cr 0n0) during timer counting, the c hange timing may conflict with the timing of the match, so the operation is not guaran teed in such cases. to change cr0n0 during timer counting, follow the procedure below using an inttm000 interrupt. chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 127 (18) edge detection <1> in the following cases, note with caution th at the valid edge of t he ti0n0 pin is detected. (a) immediately after a system reset, if a high level is input to the ti0n0 pin, the operation of the 16-bit timer counter 00 (tm00) is enabled if the rising edge or both rising and falling edges ar e specified as the valid edge of the ti0n0 pin, a rising edge is detected immediately after the tm00 operation is enabled. (b) if the tm00 operation is stop ped while the ti0n0 pin is high leve l, tm00 operation is then enabled after a low level is input to the ti0n0 pin if the falling edge or both rising and falling edges are specified as the vali d edge of the ti0n0 pin, a falling edge is detected immediately after the tm00 operation is enabled. (c) if the tm00 operation is stopped while the ti0n0 pin is low level, tm00 operation is then enabled after a high level is input to the ti0n0 pin if the rising edge or both rising and falling edges ar e specified as the valid edge, of the ti0n0 pin, a rising edge is detected immediately after the tm00 operation is enabled. remark n = 0, 1 <2> the sampling clock used to remove noise differs when a ti000 valid edge is used as the count clock and when it is used as a capture trigger. in the former case, the count clock is f xp , and in the latter case the count clock is selected by prescaler mode regist er 00 (prm00). the capture operation is not performed until the valid edge is sampled and the valid level is detected twice, thus elimin ating, noise with a short pulse width. (19) external event counter <1> the timing of the count start is after two valid edge detections. <2> when reading the external event c ounter count value, tm00 should be read. (20) ppg output <1> values in the following range should be set in cr000 and cr010: 0000h < cr010 < cr000 ffffh <2> the cycle of the pulse generated through ppg output (cr000 setting value + 1) has a duty of (cr010 setting value + 1)/(cr000 setting value + 1). (21) stop mode or system clock stop mode setting except when the valid edge of the ti000 pin is selected as the count cl ock, stop the timer operation before setting stop mode or system clock stop mode; otherwis e the timer may malfunction when the system clock starts. (22) p31/ti010/to00 pin when using p31 as the input pin (ti 010) of the valid edge, it cannot be us ed as a timer output pin (to00). when using p31 as the timer output pi n (to00), it cannot be used as the input pin (ti010) of the valid edge. chapter 6 16-bit timer/event counter 00 user?s manual u17446ej5v0ud 128 (23) external clock limitation <1> when using an input pulse of the ti000 pin as a count clock (external trigger), be sure to input the pulse width which satisfies the ac characteristi cs. for the ac characteristics, refer to chapter 22 and chapter 23 electrical specifications . <2> when an external waveform is input to 16-bit timer/ event counter 00, it is sa mpled by the noise limiter circuit and thus an error occurs on the timing to become valid inside the device. count clock (f sam ) ti000 input pulse through noise limiter circuit sampling time on filter remark the count clock (f sam ) can be selected using bits 0 and 1 (prm000, prm001) of prescaler mode register 00 (prm00). user?s manual u17446ej5v0ud 129 chapter 7 8-bit timer 80 7.1 function of 8-bit timer 80 8-bit timer 80 has an 8-bit interval timer function and ge nerates an interrupt at intervals specified in advance. table 7-1. interval time of 8-bit timer 80 minimum interval time maximum interval time resolution 2 6 /f xp (8 s) 2 14 /f xp (2.05 ms) 2 6 /f xp (8 s) 2 8 /f xp (32 s) 2 16 /f xp (8.19 ms) 2 8 /f xp (32 s) 2 10 /f xp (128 s) 2 18 /f xp (32.7 ms) 2 10 /f xp (128 s) f xp = 8.0 mhz 2 16 /f xp (8.19 ms) 2 24 /f xp (2.01 s) 2 16 /f xp (8.19 ms) 2 6 /f xp (6.4 s) 2 14 /f xp (1.64 ms) 2 6 /f xp (6.4 s) 2 8 /f xp (25.6 s) 2 16 /f xp (6.55 ms) 2 8 /f xp (25.6 s) 2 10 /f xp (102 s) 2 18 /f xp (26.2 ms) 2 10 /f xp (102 s) f xp = 10.0 mhz 2 16 /f xp (6.55 ms) 2 24 /f xp (1.68 s) 2 16 /f xp (6.55 ms) remark f xp : oscillation frequency of clock to peripheral hardware chapter 7 8-bit timer 80 user?s manual u17446ej5v0ud 130 7.2 configuration of 8-bit timer 80 8-bit timer 80 consists of the following hardware. table 7-2. configuration of 8-bit timer 80 item configuration timer counter 8-bit timer counter 80 (tm80) register 8-bit compare register 80 (cr80) control register 8-bit timer mode control register 80 (tmc80) figure 7-1. block diag ram of 8-bit timer 80 internal bus internal bus 8-bit compare register 80 (cr80) match 8-bit timer/counter 80 (tm80) clear inttm80 f xp /2 6 f xp /2 16 tce80 tcl801 tcl800 8-bit timer mode control register 80 (tmc80) f xp /2 8 f xp /2 10 selector remark f xp : oscillation frequency of clock to peripheral hardware chapter 7 8-bit timer 80 user?s manual u17446ej5v0ud 131 (1) 8-bit compare register 80 (cr80) this 8-bit register always compares its set value with the count value of 8-bit timer/counter 80 (tm80). it generates an interrupt request signal (i nttm80) if the two values match. cr80 is set by using an 8-bit memory manipulation instru ction. a value of 00h to ffh can be set to this register. reset signal generation makes the c ontents of this register undefined. figure 7-2. format of 8-bit compare register 80 (cr80) symbol cr80 address: ffcdh after reset: undefined w 76543210 caution when changing the value of cr80, be sure to stop the timer operation. if the value of cr80 is changed with the timer opera tion enabled, a match interrupt request signal is generated immediately and the ti mer may be cleared. (2) 8-bit timer counter 80 (tm80) this 8-bit register counts the count pulses. the value of tm80 can be read by using an 8-bit memory manipulation instruction. reset signal generation clears tm80 to 00h. figure 7-3. format of 8-bit timer counter 80 (tm80) symbol tm80 address: ffceh after reset: 00h r 76543210 chapter 7 8-bit timer 80 user?s manual u17446ej5v0ud 132 7.3 register controlling 8-bit timer 80 8-bit timer 80 is controlled by 8-bit timer mode control register 80 (tmc80). (1) 8-bit timer mode control register 80 (tmc80) this register is used to enable or stop the operati on of 8-bit timer/counter 80 (tm80), and to set the count clock of tm80. this register is set by using a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears tmc80 to 00h. figure 7-4. format of 8-bit timer mode control register 80 (tmc80) address: ffcch after reset: 00h r/w symbol <7> 6 5 4 3 2 1 0 tmc80 tce80 0 0 0 0 tcl801 tcl800 0 tce80 control of operation of tm80 0 stop operation (clear tm80 to 00h). 1 enable operation. selection of count clock of 8-bit timer 80 tcl801 tcl800 f xp = 8.0 mhz f xp = 10.0 mhz 0 0 f xp /2 6 125 khz 156.3 khz 0 1 f xp /2 8 31.25 khz 39.06 khz 1 0 f xp /2 10 7.81 khz 9.77 khz 1 1 f xp /2 16 0.12 khz 0.15 khz cautions 1. be sure to set tmc 80 after stopping the timer operation. 2. be sure to clear bits 0 and 6 to 0. remark f xp : oscillation frequency of clock to peripheral hardware chapter 7 8-bit timer 80 user?s manual u17446ej5v0ud 133 7.4 operation of 8-bit timer 80 7.4.1 operation as interval timer when 8-bit timer 80 operates as an interval timer, it can repeatedly generate an interrupt at intervals specified by the count value set in advance to 8-bit compare register 80 (cr80). to use 8-bit timer 80 as an interval timer, make the following setting. <1> disable the operation of 8-bit time r counter 80 (clear tce80 (bit 7 of 8-bit timer mode control register 80 (tmc80)) to 0). <2> set the count clock of 8-bit timer 80 (refer to tables 7-3 and 7-4 ). <3> set the count value to cr80. <4> enable the operation of tm80 (set tce80 to 1). when the count value of 8-bit timer counter 80 (tm80) matches the set value of cr 80, the value of tm80 is cleared to 00h and counting is continued. at the same time, an interrupt request signal (inttm80) is generated. tables 7-3 and 7-4 show the interval time, and figure 7-5 shows the timing of the interval timer operation. cautions 1. when changing the value of cr80, be sure to stop the timer operation. if the value of cr80 is changed with the timer operation enabled, a matc h interrupt request si gnal may be generated immediately. 2. if the count clock of tmc80 is set and the operation of tm80 is enabled at the same time by using an 8-bit memory manipula tion instruction, the error of one cycle after the timer is started may be 1 clock or more (refer to 7.5 (1) error when timer starts). therefore, be sure to follow the above sequence when us ing tm80 as an interval timer. table 7-3. interval time of 8-bit timer 80 (f xp = 8.0 mhz) tcl801 tcl800 minimum interval time maximum interval time resolution 0 0 2 6 /f xp (8 s) 2 14 /f xp (2.05 ms) 2 6 /f xp (8 s) 0 1 2 8 /f xp (32 s) 2 16 /f xp (8.19 ms) 2 8 /f xp (32 s) 1 0 2 10 /f xp (128 s) 2 18 /f xp (32.7 ms) 2 10 /f xp (128 s) 1 1 2 16 /f xp (8.19 ms) 2 24 /f xp (2.01 s) 2 16 /f xp (8.19 ms) remark f xp : oscillation frequency of clock to peripheral hardware table 7-4. interval time of 8-bit timer 80 (f xp = 10.0 mhz) tcl801 tcl800 minimum interval time maximum interval time resolution 0 0 2 6 /f xp (6.4 s) 2 14 /f xp (1.64 ms) 2 6 /f xp (6.4 s) 0 1 2 8 /f xp (25.6 s) 2 16 /f xp (6.55 ms) 2 8 /f xp (25.6 s) 1 0 2 10 /f xp (102 s) 2 18 /f xp (26.2 ms) 2 10 /f xp (102 s) 1 1 2 16 /f xp (6.55 ms) 2 24 /f xp (1.68 s) 2 16 /f xp (6.55 ms) remark f xp : oscillation frequency of clock to peripheral hardware chapter 7 8-bit timer 80 user?s manual u17446ej5v0ud 134 figure 7-5. timing of interval timer operation clear clear count start interval time interval time count clock tm80 count value cr80 tce80 inttm80 n 01h 00h n 01h 00h n 00h 01h nn nn t interrupt request generated interrupt request generated remark interval time = (n + 1) t n = 00h to ffh chapter 7 8-bit timer 80 user?s manual u17446ej5v0ud 135 7.5 notes on 8-bit timer 80 (1) error when timer starts the time from starting the timer to gener ation of the match signal in cludes an error of up to 1.5 clocks. this is because, if the timer is started while the count clo ck is high, the rising edge may be immediately detected and the counter may be incremented (refer to figure 7-6 ). figure 7-6. case where error of 1.5 clocks (max.) occurs 8-bit timer counter 80 (tm80) count pulse clear signal selected clock tce80 delay a delay b selected clock tce80 clear signal count pulse tm80 count value 00h 01h 02h 03h ... delay a delay b if the timer is started when the selected clock is high and if delay a > delay b, an error of up to 1.5 clocks occurs. (2) setting of 8-bit compare register 80 8-bit compare register 80 (cr80) can be set to 00h. (3) note on setting stop mode before executing the stop instruction, be sure to stop the timer operation (tce80 = 0). user?s manual u17446ej5v0ud 136 chapter 8 8-bit timer h1 8.1 functions of 8-bit timer h1 8-bit timer h1 has the following functions. ? interval timer ? pwm output mode ? square-wave output 8.2 configuration of 8-bit timer h1 8-bit timer h1 consists of the following hardware. table 8-1. configuration of 8-bit timer h1 item configuration timer register 8-bit timer counter h1 registers 8-bit timer h compare register 01 (cmp01) 8-bit timer h compare register 11 (cmp11) timer output toh1 control registers 8-bit timer h mode register 1 (tmhmd1) port mode register 4 (pm4) port register 4 (p4) figure 8-1 shows a block diagram. chapter 8 8-bit timer h1 user?s manual u17446ej5v0ud 137 figure 8-1. block diag ram of 8-bit timer h1 match selector internal bus tmhe1 cks12 cks11 cks10 tmmd11 tmmd10 tolev1 toen1 8-bit timer h mode register 1 (tmhmd1) 8-bit timer h compare register 11 (cmp11) decoder toh1/p42 inttmh1 selector f xp f xp /2 2 f xp /2 4 f xp /2 6 f xp /2 12 f rl /2 7 interrupt generator output controller level inversion 1 0 f/f r 8-bit timer counter h1 pwm mode signal timer h enable signal clear 3 2 8-bit timer h compare register 01 (cmp01) output latch (p42) pm42 chapter 8 8-bit timer h1 user?s manual u17446ej5v0ud 138 (1) 8-bit timer h compare register 01 (cmp01) this register can be read or written by an 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 8-2. format of 8-bit time r h compare register 01 (cmp01) symbol cmp01 address: ff0eh after reset: 00h r/w 7 6 5 4 32 1 0 caution cmp01 cannot be rewritte n during timer count operation. (2) 8-bit timer h compare register 11 (cmp11) this register can be read or written by an 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 8-3. format of 8-bit time r h compare register 11 (cmp11) symbol cmp11 address: ff0fh after reset: 00h r/w 7 6 5 4 32 1 0 cmp11 can be rewritten during timer count operation. if the cmp11 value is rewritten during timer operation, the co mpare value after the rewrite takes effect at the timing at which the count value and the compare value before the rewrite match. if the timing at which the count value and compare value match conflicts with the timing of the writing from the cpu to cmp11, the compare value after the rewrite takes effect at the timing at which the next count value and the com pare value before the rewrite match. caution in the pwm output mode, be sure to set cm p11 when starting the timer count operation (tmhe1 = 1) after the timer count operation was stopped (tmh e1 = 0) (be sure to set again even if setting the same value to cmp11). chapter 8 8-bit timer h1 user?s manual u17446ej5v0ud 139 8.3 registers contro lling 8-bit timer h1 the following three registers are used to control 8-bit timer h1. ? 8-bit timer h mode register 1 (tmhmd1) ? port mode register 4 (pm4) ? port register 4 (p4) (1) 8-bit timer h mode register 1 (tmhmd1) this register controls the mode of timer h. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. chapter 8 8-bit timer h1 user?s manual u17446ej5v0ud 140 figure 8-4. format of 8-bit timer h mode register 1 (tmhmd1) tmhe1 stop timer count operation (counter is cleared to 0) enable timer count operation (count operation started by inputting clock) tmhe1 0 1 timer operation enable tmhmd1 symbol cks12 cks11 cks10 tmmd11 tmmd10 tolev1 toen1 address: ff70h after reset: 00h r/w f xp f xp /2 2 f xp /2 4 f xp /2 6 f xp /2 12 f rl /2 7 cks12 0 0 0 0 1 1 cks11 0 0 1 1 0 0 cks10 0 1 0 1 0 1 (10 mhz) (2.5 mhz) (625 khz) (156.25 khz) (2.44 khz) (1.88 khz (typ.)) count clock (f cnt ) selection setting prohibited other than above interval timer mode pwm output mode setting prohibited tmmd11 0 1 tmmd10 0 0 timer operation mode low level high level tolev1 0 1 timer output level control (in default mode) disable output enable output toen1 0 1 timer output control other than above <7> 6 5 4 3 2 <1> <0> cautions 1. when tmhe1 = 1, setting the other bits of the tmhmd1 register is prohibited. 2. in the pwm output mode, be sure to set 8-bit timer h compare re gister 11 (cmp11) when starting the timer count operation (tmhe1 = 1) after the timer count operation was stopped (tmhe1 = 0) (be sure to set again even if setting the same val ue to the cmp11 register). remarks 1. f xp : oscillation frequency of clock to peripheral hardware 2. f rl : low-speed internal oscillation clock frequency 3. figures in parentheses apply to operation at f xp = 10 mhz, f rl = 240 khz (typ.). chapter 8 8-bit timer h1 user?s manual u17446ej5v0ud 141 (2) port mode register 4 (pm4) this register sets port 4 input/output in 1-bit units. when using the p42/toh1 pin for timer output, cl ear pm42 and the output latch of p42 to 0. pm4 can be set by a 1-bit or 8-bit memory manipulation instruction. generation of reset signal sets this register to ffh. figure 8-5. format of port mode register 4 (pm4) address: ff24h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm4 pm47 pm46 pm45 pm44 pm43 pm42 pm41 pm40 pm4n p4n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 8 8-bit timer h1 user?s manual u17446ej5v0ud 142 8.4 operation of 8-bit timer h1 8.4.1 operation as interval timer/square-wave output when 8-bit timer counter h1 and compare register 01 (cmp01) match, an interrupt request signal (inttmh1) is generated and 8-bit timer counter h1 is cleared to 00h. compare register 11 (cmp11) is not used in interval time r mode. since a match of 8-bit timer counter h1 and the cmp11 register is not detected even if the cmp11 register is set, timer output is not affected. by setting bit 0 (toen1) of timer h mode register 1 (tmh md1) to 1, a square wave of any frequency (duty = 50%) is output from toh1. (1) usage generates the inttmh1 signal repeatedly at the same interval. <1> set each register. figure 8-6. register setting during inte rval timer/square-wave output operation (i) setting timer h mode register 1 (tmhmd1) 0 0/1 0/1 0/1 0 0 0/1 0/1 tmmd10 tolev1 toen1 cks11 cks12 tmhe1 tmhmd1 cks10 tmmd11 timer output setting timer output level inversion setting interval timer mode setting count clock (f cnt ) selection count operation stopped (ii) cmp01 register setting ? compare value (n) <2> count operation starts when tmhe1 = 1. <3> when the values of 8-bit timer counter h1 and the cmp01 register match, the inttmh1 signal is generated and 8-bit timer counter h1 is cleared to 00h. interval time = (n +1)/f cnt <4> subsequently, the inttmh1 signal is generated at t he same interval. to stop the count operation, clear tmhe1 to 0. chapter 8 8-bit timer h1 user?s manual u17446ej5v0ud 143 (2) timing chart the timing of the interval timer/square- wave output operation is shown below. figure 8-7. timing of interval time r/square-wave output operation (1/2) (a) basic operation (01h cmp01 feh) 00h count clock count start 8-bit timer counter h1 cmp01 tmhe1 inttmh1 toh1 01h n clear interval time clear n 00h 01h n 00h 01h 00h <2> level inversion, match interrupt occurrence, 8-bit timer counter h1 clear <2> level inversion, match interrupt occurrence, 8-bit timer counter h1 clear <3> <1> <1> the count operation is enabled by setting the tmhe1 bi t to 1. the count clock starts counting no more than 1 clock after the operation is enabled. <2> when the values of 8-bit timer count er h1 and the cmp01 register match, the value of 8-bit timer counter h1 is cleared, the toh1 output level is in verted, and the inttmh1 signal is output. <3> the inttmh1 signal and toh1 output become inactive by clearing the tmhe1 bit to 0 during timer h1 operation. if these are inactive from the first, the level is retained. remark 01h n feh chapter 8 8-bit timer h1 user?s manual u17446ej5v0ud 144 figure 8-7. timing of interval time r/square-wave output operation (2/2) (b) operation when cmp01 = ffh 00h count clock count start 8-bit timer counter h1 cmp01 tmhe1 inttmh1 toh1 01h feh clear clear ffh 00h feh ffh 00h ffh interval time (c) operation when cmp01 = 00h count clock count start 8-bit timer counter h1 cmp01 tmhe1 inttmh1 toh1 00h 00h interval time chapter 8 8-bit timer h1 user?s manual u17446ej5v0ud 145 8.4.2 operation as pwm output mode in pwm output mode, a pulse with an arbi trary duty and arbitrary cycle can be output. 8-bit timer compare register 01 (cmp01) controls the cycle of timer output (toh1). re writing the cmp01 register during timer operation is prohibited. 8-bit timer compare register 11 (cmp11) controls the dut y of timer output (toh1). re writing the cmp11 register during timer operation is possible. the operation in pwm output mode is as follows. toh1 output becomes active and 8-bit timer counter h1 is cleared to 0 when 8-bit timer counter h1 and the cmp01 register match after the timer count is started. toh1 output becomes inactive when 8-bit timer counter h1 and the cmp11 register match. (1) usage in pwm output mode, a pulse for which an arbitr ary duty and arbitrary cycle can be set is output. <1> set each register. figure 8-8. register setting in pwm output mode (i) setting timer h mode register 1 (tmhmd1) 0 0/1 0/1 0/1 1 0 0/1 1 tmmd10 tolev1 toen1 cks11 cks12 tmhe1 tmhmd1 cks10 tmmd11 timer output enabled timer output level inversion setting pwm output mode selection count clock (f cnt ) selection count operation stopped (ii) setting cmp01 register ? compare value (n): cycle setting (iii) setting cmp11 register ? compare value (m): duty setting remark 00h cmp11 (m) < cmp01 (n) ffh <2> the count operation starts when tmhe1 = 1. <3> the cmp01 register is the compare register that is to be compared firs t after count operation is enabled. when the values of 8-bit timer counter h1 and the cmp0 1 register match, 8-bit timer counter h1 is cleared, an interrupt request signal (inttmh1) is generated, and toh1 output becomes active. at the same time, the compare register to be compared with 8-bit timer c ounter h1 is changed from t he cmp01 register to the cmp11 register. chapter 8 8-bit timer h1 user?s manual u17446ej5v0ud 146 <4> when 8-bit timer counter h1 and the cmp11 regist er match, toh1 output becomes inactive and the compare register to be compared with 8-bit timer coun ter h1 is changed from the cmp11 register to the cmp01 register. at this time, 8-bit timer counter h1 is not cleared and the inttmh1 signal is not generated. <5> by performing procedures <3> and <4> repeatedl y, a pulse with an arbitrary duty can be obtained. <6> to stop the count operation, set tmhe1 = 0. if the setting value of the cmp01 register is n, the setting value of the cmp11 register is m, and the count clock frequency is f cnt , the pwm pulse output cycle and duty are as follows. pwm pulse output cycle = (n+1)/f cnt duty = active width : total widt h of pwm = (m + 1) : (n + 1) cautions 1. in pwm output mode, the setting value fo r the cmp11 register can be changed during timer count operation. however, th ree operation clocks (signal selected using the cks12 to cks10 bits of the tmhmd1 register) or more are required to transfer the register value after rewriting the cmp11 register value. 2. be sure to set th e cmp11 register when starting the ti mer count operation (tmhe1 = 1) after the timer count operation was stopped (tmhe1 = 0) (be sure to set again even if setting the same value to the cmp11 register). chapter 8 8-bit timer h1 user?s manual u17446ej5v0ud 147 (2) timing chart the operation timing in pwm output mode is shown below. caution make sure that the cmp11 register setting value (m) and cmp01 register setting value (n) are within the following range. 00h cmp11 (m) < cmp01 (n) ffh figure 8-9. operation timing in pwm output mode (1/4) (a) basic operation (00h < cmp11 < cmp01 < ffh) count clock 8-bit timer counter h1 cmp01 tmhe1 inttmh1 toh1 (tolev1 = 0) toh1 (tolev1 = 1) 00h 01h a5h 00h 01h 02h a5h 00h a5h 00h 01h 02h cmp11 a5h 01h <1> <2> <3> <4> <1> the count operation is enabled by setting the tmhe1 bit to 1. start 8-bit timer counter h1 by masking one count clock to count up. at this time, toh1 output remains inactive (when tolev1 = 0). <2> when the values of 8-bit timer counter h1 and the cm p01 register match, the toh1 output level is inverted, the value of 8-bit timer counter h1 is cleared, and the inttmh1 signal is output. <3> when the values of 8-bit timer counter h1 and the cm p11 register match, the le vel of the toh1 output is returned. at this time, the 8-bit timer counter val ue is not cleared and the inttmh1 signal is not output. <4> clearing the tmhe1 bit to 0 during timer h1 operati on makes the inttmh1 signal and toh1 output inactive. chapter 8 8-bit timer h1 user?s manual u17446ej5v0ud 148 figure 8-9. operation timing in pwm output mode (2/4) (b) operation when cm p01 = ffh, cmp11 = 00h count clock 8-bit timer counter h1 cmp01 tmhe1 inttmh1 toh1 (tolev1 = 0) 00h 01h ffh 00h 01h 02h ffh 00h ffh 00h 01h 02h cmp11 ffh 00h (c) operation when cmp01 = ffh, cmp11 = feh count clock 8-bit timer counter h1 cmp01 tmhe1 inttmh1 toh1 (tolev1 = 0) 00h 01h feh ffh 00h 01h feh ffh 00h 01h feh ffh 00h cmp11 ffh feh chapter 8 8-bit timer h1 user?s manual u17446ej5v0ud 149 figure 8-9. operation timing in pwm output mode (3/4) (d) operation when cmp01 = 01h, cmp11 = 00h count clock 8-bit timer counter h1 cmp01 tmhe1 inttmh1 toh1 (tolev1 = 0) 01h 00h 01h 00h 01h 00h 00h 01h 00h 01h cmp11 00h chapter 8 8-bit timer h1 user?s manual u17446ej5v0ud 150 figure 8-9. operation timing in pwm output mode (4/4) (e) operation by changing cmp11 (cmp11 = 02h 03h, cmp01 = a5h) cmp01 tmhe1 inttmh1 toh1 (tolev1 = 0) 00h 01h 02h a5h 00h 01h 02h 03h a5h 00h 01h 02h 03h a5h 00h cmp11 02h a5h 03h 02h (03h) 80h count clock 8-bit timer counter h1 <2>' <2> <1> <3> <4> <5> <6> <1> the count operation is enabled by setting tmhe1 = 1. start 8-bit timer counter h1 by masking one count clock to count up. at this time, the toh1 output remains inactive (when tolev1 = 0). <2> the cmp11 register value can be changed during timer counter operation. this operation is asynchronous to the count clock. <3> when the values of 8-bit timer count er h1 and the cmp01 register match, the value of 8-bit timer counter h1 is cleared, the toh1 output becomes active, and the inttmh1 signal is output. <4> if the cmp11 register value is changed, the value is latched and not transferred to the register. when the values of 8-bit timer counter h1 and the cmp11 register before the change match, the value is transferred to the cmp11 register and the cmp11 re gister value is changed (<2>?). however, three count clocks or more are required fr om when the cmp11 register value is changed to when the value is transferred to the register. if a match signal is generated within thr ee count clocks, the changed value cannot be transferred to the register. <5> when the values of 8-bit timer counter h1 and the cm p11 register after the change match, the toh1 output becomes inactive. 8-bit timer counter h1 is no t cleared and the inttmh1 signal is not generated. <6> clearing the tmhe1 bit to 0 during timer h1 operati on makes the inttmh1 signal and toh1 output inactive. user?s manual u17446ej5v0ud 151 chapter 9 watchdog timer 9.1 functions of watchdog timer the watchdog timer is used to detect an inadvertent program loop. if a program loop is detected, an internal reset signal is generated. when a reset occurs due to the watchdog timer, bit 4 (wdtrf) of the reset control flag register (resf) is set to 1. for details of resf, see chapter 15 reset function . table 9-1. loop detection time of watchdog timer loop detection time during low-speed internal oscillation clock operation during system clock operation 2 11 /f rl (4.27 ms) 2 13 /f x (819.2 s) 2 12 /f rl (8.53 ms) 2 14 /f x (1.64 ms) 2 13 /f rl (17.07 ms) 2 15 /f x (3.28 ms) 2 14 /f rl (34.13 ms) 2 16 /f x (6.55 ms) 2 15 /f rl (68.27 ms) 2 17 /f x (13.11 ms) 2 16 /f rl (136.53 ms) 2 18 /f x (26.21 ms) 2 17 /f rl (273.07 ms) 2 19 /f x (52.43 ms) 2 18 /f rl (546.13 ms) 2 20 /f x (104.86 ms) remarks 1. f rl : low-speed internal oscillation clock frequency 2. f x : system clock oscillation frequency 3. figures in parentheses apply to operation at f rl = 480 khz (max.), f x = 10 mhz. the operation mode of the watchdog time r (wdt) is switched according to t he option byte setting of the on-chip low-speed internal oscillator as shown in table 9-2. chapter 9 watchdog timer user?s manual u17446ej5v0ud 152 table 9-2. option byte setting an d watchdog timer operation mode option byte setting low-speed internal oscillator cannot be stopped low-speed internal oscillator can be stopped by software watchdog timer clock source fixed to f rl note 1 . ? selectable by software (f x , f rl or stopped) ? when reset is released: f rl operation after reset operation star ts with the maximum interval (2 18 /f rl ). operation starts with the maximum interval (2 18 /f rl ). operation mode selection the interval can be changed only once. the clock selection/interval can be changed only once. features the watchdog timer cannot be stopped. the watchdog timer can be stopped note 2 . notes 1. as long as power is being supplied, low-speed intern al oscillator cannot be stopped (except in the reset period). 2. the conditions under which clock supply to t he watchdog timer is stopped differ depending on the clock source of the watchdog timer. <1> if the clock source is f x , clock supply to the watchdog timer is stopped under the following conditions. ? when f x is stopped ? in halt/stop mode ? during oscillation stabilization time <2> if the clock source is f rl , clock supply to the watchdog timer is stopped under the following conditions. ? if the cpu clock is f x and if f rl is stopped by software before exec ution of the stop instruction ? in halt/stop mode remarks 1. f rl : low-speed internal oscillation clock frequency 2. f x : system clock oscillation frequency chapter 9 watchdog timer user?s manual u17446ej5v0ud 153 9.2 configuration of watchdog timer the watchdog timer consists of the following hardware. table 9-3. configuration of watchdog timer item configuration control registers watchdog timer mode register (wdtm) watchdog timer enable register (wdte) figure 9-1. block diagram of watchdog timer clock input controller output controller internal reset signal wdcs2 internal bus wdcs1 wdcs0 wdcs3 wdcs4 01 1 selector 16-bit counter or 2 13 /f x to 2 20 /f x watchdog timer enable register (wdte) watchdog timer mode register (wdtm) 3 2 clear option byte (to set ?low-speed internal oscillator cannot be stopped? or ?low-speed internal oscillator can be stopped by software?) f rl /2 2 f x /2 4 2 11 /f rl to 2 18 /f rl remarks 1. f rl : low-speed internal oscillation clock frequency 2. f x : system clock oscillation frequency chapter 9 watchdog timer user?s manual u17446ej5v0ud 154 9.3 registers controlling watchdog timer the watchdog timer is controlled by the following two registers. ? watchdog timer mode register (wdtm) ? watchdog timer enable register (wdte) (1) watchdog timer mode register (wdtm) this register sets the overflow time and operation clock of the watchdog timer. this register can be set by an 8-bit memory manipula tion instruction and can be read many times, but can be written only once after reset is released. generation of reset signal sets this register to 67h. figure 9-2. format of watchdog timer mode register (wdtm) 0 wdcs0 1 wdcs1 2 wdcs2 3 wdcs3 4 wdcs4 5 1 6 1 7 0 symbol wdtm address: ff48h after reset: 67h r/w wdcs4 note 1 wdcs3 note 1 operation clock selection 0 0 low-speed internal oscillation clock (f rl ) 0 1 system clock (f x ) 1 watchdog timer operation stopped overflow time setting wdcs2 note 2 wdcs1 note 2 wdcs0 note 2 during low-speed internal oscillation clock operation during system clock operation 0 0 0 2 11 /f rl (4.27 ms) 2 13 /f x (819.2 s) 0 0 1 2 12 /f rl (8.53 ms) 2 14 /f x (1.64 ms) 0 1 0 2 13 /f rl (17.07 ms) 2 15 /f x (3.28 ms) 0 1 1 2 14 /f rl (34.13 ms) 2 16 /f x (6.55 ms) 1 0 0 2 15 /f rl (68.27 ms) 2 17 /f x (13.11 ms) 1 0 1 2 16 /f rl (136.53 ms) 2 18 /f x (26.21 ms) 1 1 0 2 17 /f rl (273.07 ms) 2 19 /f x (52.43 ms) 1 1 1 2 18 /f rl (546.13 ms) 2 20 /f x (104.86 ms) notes 1. if ?low-speed internal oscillator cannot be stopped? is specified by the option byte, this cannot be set. the low-speed internal oscillation clock will be selected no matter what value is written. 2. reset is released at the maximu m cycle (wdcs2, 1, 0 = 1, 1, 1). chapter 9 watchdog timer user?s manual u17446ej5v0ud 155 cautions 1. set bits 7, 6, and 5 to 0, 1, and 1, respectively . do not set the other values. 2. after reset is released, wdtm can be written only once by an 8-bit memory manipulation instruction. if writing is attempted a second time, an internal reset signal is generated. however, at the first write, if ?1? and ?x? are set for wdcs4 and wdcs3 respectively and the watchdog timer is stopped, then the internal reset signal does not occur even if the following are executed. ? second write to wdtm ? 1-bit memory manipulation instruction to wdte ? writing of a value othe r than ?ach? to wdte 3. wdtm cannot be set by a 1-bi t memory manipulation instruction. 4. when using the flash memory progra mming by self programming, set the overflow time for the watchdog timer so that enough overflow time is secured (example 1- byte writing: 200 s min., 1-block deletion: 10 ms min.). remarks 1. f rl : low-speed internal oscillation clock frequency 2. f x : system clock oscillation frequency 3. : don?t care 4. figures in parentheses apply to operation at f rl = 480 khz (max.), f x = 10 mhz. (2) watchdog timer enable register (wdte) writing ach to wdte clears the watchdog timer counter and starts counting again. this register can be set by an 8-bit memory manipulation instruction. generation of reset signal sets this register to 9ah. figure 9-3. format of watchdog timer enable register (wdte) 0 1 2 3 4 5 6 7 symbol wdte address: ff49h after reset: 9ah r/w cautions 1. if a value other than ach is written to wdte, an internal reset signal is generated. 2. if a 1-bit memory mani pulation instruction is executed for wdte, an internal reset signal is generated. 3. the value read from wd te is 9ah (this differs from the written value (ach)). chapter 9 watchdog timer user?s manual u17446ej5v0ud 156 9.4 operation of watchdog timer 9.4.1 watchdog timer operation when ?low-speed intern al oscillator cannot be stopped? is selected by option byte the operation clock of watchdog timer is fixed to low-speed internal oscillation clock. after reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (wdcs2, w dcs1, wdcs0) of the watchdog timer mode register (wdtm) = 1, 1, 1) . the watchdog timer operation cannot be stopped. the following shows the watchdog timer operation after reset release. 1. the status after reset release is as follows. ? operation clock: low-speed internal oscillation clock ? cycle: 2 18 /f rl (546.13 ms: operation with f rl = 480 khz (max.)) ? counting starts 2. the following should be set in the watchdog timer mode register (wdtm) by an 8-bit memory manipulation instruction notes 1, 2 . ? cycle: set using bits 2 to 0 (wdcs2 to wdcs0) 3. after the above procedures are exec uted, writing ach to wdte clears the count to 0, enabling recounting. notes 1. the operation clock (low-speed internal oscillation clo ck) cannot be changed. if any value is written to bits 3 and 4 (wdcs3, wdcs4) of wdtm, it is ignored. 2. as soon as wdtm is written, the c ounter of the watchdog timer is cleared. caution in this mode, ope ration of the watchdog timer cannot be stopped even during stop instruction execution. for 8-bit timer h1 (tmh1), a division of the low-speed internal oscillation clock can be selected as the count source, so clear the watchdog timer using th e interrupt request of tmh1 before the watchdog timer overfl ows after stop instruction executi on. if this processing is not performed, an internal reset si gnal is generated when the watc hdog timer overflows after stop instruction execution. a status transition diagram is shown below chapter 9 watchdog timer user?s manual u17446ej5v0ud 157 figure 9-4. status transition diagram when ? low-speed internal oscillator cannot be stopped? is selected by option byte reset wdt clock: f rl overflow time: 546.13 ms (max.) stop wdt count continues. halt wdt count continues. stop instruction halt instruction wdt clock is fixed to f rl . select overflow time (settable only once). wdt clock: f rl overflow time: 4.27 ms to 546.13 ms (max.) wdt count continues. interrupt interrupt wdte = ?ach? clear wdt counter. chapter 9 watchdog timer user?s manual u17446ej5v0ud 158 9.4.2 watchdog timer operation when ?low-speed inte rnal oscillator can be stopped by software? is selected by option byte the operation clock of the watchdog timer can be selected as either the low-spe ed internal oscillation clock or the system clock. after reset is released, operation is st arted at the maximum cycle of the low-spe ed internal oscillation clock (bits 2, 1, and 0 (wdcs2, wdcs1, wdcs0) of the watchdo g timer mode register (wdtm) = 1, 1, 1). the following shows the watchdog timer operation after reset release. 1. the status after reset release is as follows. ? operation clock: low-speed internal oscillation clock ? cycle: 2 18 /f rl (546.13 ms: operation with f rl = 480 khz (max.)) ? counting starts 2. the following should be set in the watchdog timer mode register (wdtm) by an 8-bit memory manipulation instruction notes 1, 2, 3 . ? operation clock: any of the following can be selected using bits 3 and 4 (wdcs3 and wdcs4). low-speed internal oscillation clock (f rl ) system clock (f x ) watchdog timer operation stopped ? cycle: set using bits 2 to 0 (wdcs2 to wdcs0) 3. after the above procedures are exec uted, writing ach to wdte clears the count to 0, enabling recounting. notes 1. as soon as wdtm is written, the count er of the watchdog timer is cleared. 2. set bits 7, 6, and 5 to 0, 1, 1, res pectively. do not set the other values. 3. at the first write, if the watchdog time r is stopped by setting wdcs4 and wdcs3 to 1 and , respectively, an internal reset signal is not gener ated even if the following processing is performed. ? wdtm is written a second time. ? a 1-bit memory manipulation instruction is executed to wdte. ? a value other than ach is written to wdte. caution in this mode, watchdog timer operation is stop ped during halt/stop in struction execution. after halt/stop mode is released, counting is started agai n using the operation clock of the watchdog timer set before halt/stop instruction execution by wdtm. at this time, the counter is not cleared to 0 but holds its value. for the watchdog timer operation during stop mode and halt mode in each status, see 9.4.3 watchdog timer operation in stop mode (when ?low-speed internal o scillator can be stopped by software? is selected by option byte) and 9.4.4 watchdog timer operation in halt mode (when ?low-speed internal oscillator can be stopped by software? is selected by option byte) . a status transition diagram is shown below. chapter 9 watchdog timer user?s manual u17446ej5v0ud 159 figure 9-5. status transition diagram when ?low -speed internal oscillator can be stopped by software? is selected by option byte reset wdt clock: f rl overflow time: 546.13 ms (max.) wdt clock = f rl select overflow time (settable only once). wdt clock: f rl overflow time: 4.27 ms to 546.13 ms (max.) wdt count continues. stop wdt count stops. halt wdt count stops. stop instruction halt instruction interrupt interrupt wdte = ?ach? clear wdt counter. wdt operation stops. wdcs4 = 1 wdt clock: f x overflow time: 2 13 /f x to 2 20 /f x wdt count continues. wdt clock = f x select overflow time (settable only once). wdt clock: f rl wdt count stops. wdte = ?ach? clear wdt counter. lsrstop = 1 lsrstop = 0 stop wdt count stops. halt wdt count stops. stop instruction halt instruction interrupt interrupt stop instruction interrupt interrupt halt instruction wdte = ?ach? clear wdt counter. chapter 9 watchdog timer user?s manual u17446ej5v0ud 160 9.4.3 watchdog timer operation in stop mode (when ?l ow-speed internal oscillator can be stopped by software? is selected by option byte) the watchdog timer stops counting durin g stop instruction execution regardl ess of whether the system clock or low-speed internal oscillation clock is being used. (1) when the watchdog timer operation clock is the clock to peripheral hardware (f x ) when the stop instruction is executed when stop instruction is executed, o peration of the watchdog timer is stopp ed. after stop mode is released, operation stops for 34 s (typ.) (after waiting for the oscillation stabilization time set by the oscillation stabilization time select register (ost s) after operation stops in the case of crystal/ceramic oscillation) and then counting is started again usin g the operation clock before the operation was stopped. at this time, the counter is not cleared to 0 but holds its value. figure 9-6. operation in stop mode (wdt op eration clock: clock to peripheral hardware) <1> cpu clock: crystal/ ceramic oscillation clock operation stopped operating oscillation stabilization time normal operation stop oscillation stabilization time (set by osts register) oscillation stopped watchdog timer operating f cpu cpu operation normal operation operation stopped note <2> cpu clock: high-speed internal oscillation clo ck or external clock input operation stopped operating normal operation oscillation stopped watchdog timer f cpu cpu operation stop operating normal operation operation stopped note note the operation stop time is 17 s (min.), 34 s (typ.), and 67 s (max.). chapter 9 watchdog timer user?s manual u17446ej5v0ud 161 (2) when the watchdog timer operation clock is the low-speed internal oscillation clock (f rl ) when the stop instruction is executed when the stop instruction is execut ed, operation of the watchdog timer is stopped. after stop mode is released, operation stops for 34 s (typ.) and then counting is started a gain using the operation clock before the operation was stopped. at this time, the counter is not cleared to 0 but holds its value. figure 9-7. operation in stop mode (wdt operat ion clock: low-speed internal oscillation clock) <1> cpu clock: crystal/ ceramic oscillation clock operating oscillation stabilization time normal operation oscillation stabilization time (set by osts register) watchdog timer operation stopped operating f rl f cpu cpu operation normal operation stop oscillation stopped operation stopped note <2> cpu clock: high-speed internal oscillation clo ck or external clock input operating normal operation watchdog timer operation stopped operating f rl f cpu cpu operation normal operation stop oscillation stopped operation stopped note note the operation stop time is 17 s (min.), 34 s (typ.), and 67 s (max.). chapter 9 watchdog timer user?s manual u17446ej5v0ud 162 9.4.4 watchdog timer operation in ha lt mode (when ?low-speed intern al oscillator can be stopped by software? is selected by option byte) the watchdog timer stops counting during halt instruction execution regardless of whether the operation clock of the watchdog timer is the system clock (f x ) or low-speed internal oscillation clock (f rl ). after halt mode is released, counting is started again using the operation clock before the operation was stopped. at th is time, the counter is not cleared to 0 but holds its value. figure 9-8. operation in halt mode watchdog timer operating f x or f rl f cpu cpu operation normal operation operating halt operation stopped normal operation user?s manual u17446ej5v0ud 163 chapter 10 a/d converter 10.1 functions of a/d converter the a/d converter converts an analog input signal into a digital value, and consis ts of up to four channels (ani0 to ani3) with a resolution of 10 bits. the a/d converter has the following function. ? 10-bit resolution a/d conversion 10-bit resolution a/d conversion is carried out repeatedly for one channel selected from analog inputs ani0 to ani3. each time an a/d conversion operation en ds, an interrupt request (intad) is generated. figure 10-1 shows the timing of sampling and a/d conv ersion, and table 10-1 shows the sampling time and a/d conversion time. figure 10-1. timing of a/d con verter sampling and a/d conversion adcs conversion time conversion time sampling time sampling timing intad adcs 1 or ads rewrite sampling time note note 2 or 3 clocks are required from the adcs rising to sampling start. chapter 10 a/d converter user?s manual u17446ej5v0ud 164 table 10-1. sampling time and a/d conversion time f xp = 8 mhz f xp = 10 mhz reference voltage range note 1 sampling time note 2 conversion time note 3 sampling time note 2 conversion time note 3 sampling time note 2 conversion time note 3 fr2 fr1 fr0 av ref 4.5 v 12/f xp 36/f xp 1.5 s 4.5 s 1.2 s 3.6 s 0 0 0 av ref 4.0 v 24/f xp 72/f xp 3.0 s 9.0 s 2.4 s 7.2 s 1 0 0 96/f xp 144/f xp 12.0 s 18.0 s 9.6 s 14.4 s 1 1 0 48/f xp 96/f xp 6.0 s 12.0 s 4.8 s 9.6 s 1 0 1 48/f xp 72/f xp 6.0 s 9.0 s 4.8 s 7.2 s 0 1 0 av ref 2.85 v 24/f xp 48/f xp 3.0 s 6.0 s setting prohibited note 4 (2.4 s) setting prohibited note 4 (4.8 s) 0 0 1 176/f xp 224/f xp 22.0 s 28.0 s 17.6 s 22.4 s 1 1 1 av ref 2.7 v 88/f xp 112/f xp 11.0 s 14.0 s setting prohibited note 4 (8.8 s) setting prohibited note 4 (11.2 s) 0 1 1 notes 1. be sure to set the fr2, fr1, and fr0, in accordance with the reference voltage so that notes 2 and 3 below are satisfied. example when av ref 2.7 v, f xp = 8 mhz ? the sampling time is 11.0 s or more and the a/d conversion time is 14.0 s or more and 100 s or less. ? set fr2, fr1, and fr0 = 0, 1, 1 or 1, 1, 1. 2. set the sampling time as follows. ? av ref 4.5 v: 1.0 s or more ? av ref 4.0 v: 2.4 s or more ? av ref 2.85 v: 3.0 s or more ? av ref 2.7 v: 11.0 s or more 3. set the a/d conversion time as follows. ? av ref 4.5 v: 3.0 s or more and less than 100 s ? av ref 4.0 v: 4.8 s or more and less than 100 s ? av ref 2.85 v: 6.0 s or more and less than 100 s ? av ref 2.7 v: 14.0 s or more and less than 100 s 4. setting is prohibited because the va lues do not satisfy the condition of notes 2 or 3 . caution the above sampling time and conversion time do not include the cl ock frequency error. select the sampling time and conversion time such that not es 2 and 3 above are satisf ied, while taking the clock frequency error into consider ation (an error margin maximum of 5% when using the high- speed internal oscillator). remarks 1. f xp : oscillation frequency of clock to peripheral hardware 2. the conversion time refers to the total of the sa mpling time and the time from successively comparing with the sampling value until the conversion result is output. chapter 10 a/d converter user?s manual u17446ej5v0ud 165 figure 10-2 shows the block diagram of a/d converter. figure 10-2. block diag ram of a/d converter av ref av ss intad 2 ads1 ads0 av ss ani0/p20 ani1/p21 ani2/p22 ani3/p23 adcs fr2 fr1 adce fr0 3 sample & hold circuit voltage comparator controller a/d conversion result register (adcr, adcrh) analog input channel specification register (ads) a/d converter mode register (adm) internal bus successive approximation register (sar) selector d/a converter 10.2 configuration of a/d converter the a/d converter consists of the following hardware. (1) ani0 to ani3 pins these are the analog input pins of the 4- channel a/d converter. they input analog signals to be converted into digital signals. pins other than t he one selected as the analog input pin by the analog input channel specification register (ads) can be used as i/o port pins. (2) sample & hold circuit the sample & hold circuit samples the input signal of the analog input pin selected by the selector when a/d conversion is started, and holds the sampled anal og input voltage value during a/d conversion. (3) d/a converter the d/a converter is connected between av ref and av ss , and generates a voltage to be compared with the analog input signal. (4) voltage comparator the voltage comparator compares the sampled analog input voltage and the out put voltage of the d/a converter. chapter 10 a/d converter user?s manual u17446ej5v0ud 166 (5) successive approximation register (sar) this register compares the sampled analog voltage and the voltage of the d/a converte r, and converts the result, starting from the most significant bit (msb). when the voltage value is converted into a digital valu e down to the least significant bit (lsb) (end of a/d conversion), the contents of the sar register are transfe rred to the a/d conversion result register (adcr). (6) 10-bit a/d conversion r esult register (adcr) the result of a/d conversion is loaded from the successive approximation r egister to this register each time a/d conversion is completed, and the adcr regi ster holds the result of a/d conversi on in its lower 10 bits (the higher 6 bits are fixed to 0). (7) 8-bit a/d conversion result register (adcrh) the result of a/d conversion is loaded from the successive approximation r egister to this register each time a/d conversion is completed, and the adcrh register holds th e result of a/d conversion in its higher 8 bits. (8) controller when a/d conversion has been comp leted, intad is generated. (9) av ref pin this pin inputs an analog power/reference voltage to the a/d converter. when the a/ d converter is not used, connect this pin to v dd . the signal input to ani0 to ani3 is converted into a digital signal, based on the voltage applied across av ref and av ss . (10) av ss pin this is the ground potential pin of the a/d converter. always use this pin at the same potential as that of the v ss pin even when the a/d converter is not used. (11) a/d converter mode register (adm) this register is used to set the conver sion time of the analog input signal to be converted, and to start or stop the conversion operation. (12) analog input channel sp ecification register (ads) this register is used to specify the port that inputs the analog voltage to be converted into a digital signal. (13) port mode control register 2 (pmc2) this register is used when the p20/ani0 to p23/ani3 pins are used as the analog input pi ns of the a/d converter. chapter 10 a/d converter user?s manual u17446ej5v0ud 167 10.3 registers used by a/d converter the a/d converter uses the following six registers. ? a/d converter mode register (adm) ? analog input channel specification register (ads) ? 10-bit a/d conversion result register (adcr) ? 8-bit a/d conversion result register (adcrh) ? port mode control register 2 (pmc2) ? port mode register 2 (pm2) chapter 10 a/d converter user?s manual u17446ej5v0ud 168 (1) a/d converter mode register (adm) this register sets the conversion time for analog inpu t to be a/d converted, and starts/stops conversion. adm can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 10-3. format of a/d converter mode register (adm) address: ff80h after reset: 00h r/w symbol <7> 6 5 4 3 2 1 <0> adm adcs 0 fr2 fr1 fr0 0 0 adce adcs a/d conversion operation control 0 stops conversion operation 1 note 1 starts conversion operation f xp = 8 mhz f xp = 10 mhz fr2 fr1 fr0 reference voltage range note 2 sampling time note 3 conversion time note 4 sampling time note 3 conversion time note 4 sampling time note 3 conversion time note 4 0 0 0 av ref 4.5 v 12/f xp 36/f xp 1.5 s 4.5 s 1.2 s 3.6 s 1 0 0 av ref 4.0 v 24/f xp 72/f xp 3.0 s 9.0 s 2.4 s 7.2 s 1 1 0 96/f xp 144/f xp 12.0 s 18.0 s 9.6 s 14.4 s 1 0 1 48/f xp 96/f xp 6.0 s 12.0 s 4.8 s 9.6 s 0 1 0 48/f xp 72/f xp 6.0 s 9.0 s 4.8 s 7.2 s 0 0 1 av ref 2.85 v 24/f xp 48/f xp 3.0 s 6.0 s setting prohibited note 5 (2.4 s) setting prohibited note 5 (4.8 s) 1 1 1 176/f xp 224/f xp 22.0 s 28.0 s 17.6 s 22.4 s 0 1 1 av ref 2.7 v 88/f xp 112/f xp 11.0 s 14.0 s setting prohibited note 5 (8.8 s) setting prohibited note 5 (11.2 s) adce comparator operation control note 6 0 note 1 stops operation of comparator 1 enables operation of comparator remarks 1. f xp : oscillation frequency of clock to peripheral hardware 2. the conversion time refers to the total of the sampling time and the time from successively comparing with the sampling value unt il the conversion result is output. note 1. even when the adce = 0 (comparator operation st opped), the a/d conversi on operation starts if the adcs is set to 1. however, the first conv ersion data is out of the guaranteed-value range, so ignore it. chapter 10 a/d converter user?s manual u17446ej5v0ud 169 notes 2. be sure to set the fr2, fr1, and fr0, in ac cordance with the reference voltage so that notes 3 and 4 below are satisfied. example when av ref 2.7 v, f xp = 8 mhz ? the sampling time is 11.0 s or more and the a/d conversion time is 14.0 s or more and 100 s or less. ? set fr2, fr1, and fr0 = 0, 1, 1 or 1, 1, 1. 3. set the sampling time as follows. ? av ref 4.5 v: 1.0 s or more ? av ref 4.0 v: 2.4 s or more ? av ref 2.85 v: 3.0 s or more ? av ref 2.7 v: 11.0 s or more 4. set the a/d conversion time as follows. ? av ref 4.5 v: 3.0 s or more and less than 100 s ? av ref 4.0 v: 4.8 s or more and less than 100 s ? av ref 2.85 v: 6.0 s or more and less than 100 s ? av ref 2.7 v: 14.0 s or more and less than 100 s 5. setting is prohibited because the va lues do not satisfy the condition of notes 3 or 4 . 6. the operation of the compar ator is controlled by adcs and adce, and it takes 1 s from operation start to operation stab ilization. therefore, when adcs is set to 1 after 1 s or more has elapsed from the time adce is set to 1, the conversion result at that time has priority over the first conversion result. if the adcs is set to 1 without waiting for 1 s or longer, ignore the first conversion data. table 10-2. settings of adcs and adce adcs adce a/d co nversion operation 0 0 stop status (dc power consumption path does not exist) 0 1 conversion waiting mode (only comparator consumes power) 1 conversion mode figure 10-4. timing chart wh en comparator is used adce comparator adcs conversion operation conversion operation conversion stopped conversion waiting comparator operating note note the time from the rising of the adce bit to the rising of the adcs bit must be 1 s or longer to stabilize the internal circuit. caution 1. the above sampling time and conversion time do not incl ude the clock frequency error. select the sampling time and conversion time such that notes 3 and 4 above are satisfied, while taking the clock freque ncy error into consideration (an error margin maximum of 5% when using the high-speed internal oscillator). chapter 10 a/d converter user?s manual u17446ej5v0ud 170 cautions 2. if a bit other than adcs of adm is ma nipulated while a/d conversi on is stopped (adcs = 0) and then a/d conversion is started, execute two nop instructions or an instruction equivalent to two machine cycles, and set adcs to 1. 3. a/d conversion must be stopped (adcs = 0) before rewriting bits fr0 to fr2. 4. be sure to clear bits 6, 2, and 1 to 0. (2) analog input channel specification register (ads) this register specifies the input port of the analog voltage to be a/d converted. ads can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 10-5. format of analog input channel specification register (ads) ads0 ads1 0 0 0 0 0 0 analog input channel specification ani0 ani1 ani2 ani3 ads0 0 1 0 1 ads1 0 0 1 1 0 1 2 3 4 5 6 7 ads address: ff81h after reset: 00h r/w symbol caution be sure to clear bits 2 to 7 of ads to 0. (3) 10-bit a/d conversion r esult register (adcr) this register is a 16-bit register that stores the a/d conversion result. the hi gher six bits are fixed to 0. each time a/d conversion ends, the conversion result is load ed from the successive approximation register, and is stored in adcr in order starting from bit 1 of ff19h. ff19h indicates the hi gher 2 bits of the conversion result, and ff18h indicates the lower 8 bits of the conversion result. adcr can be read by a 16-bit memory manipulation instruction. reset signal generation makes adcr undefined. figure 10-6. format of 10-bit a/d conversion result register (adcr) symbol address: ff18h, ff19h after reset: undefined r ff19h ff18h 0 0 0 0 0 0 adcr caution when writing to the a/d converter mode re gister (adm) and analog i nput channel specification register (ads), the contents of adcr may beco me undefined. read the conversion result following conversion completion before writing to adm and ads. using timing other than the above may cause an incorrect c onversion result to be read. chapter 10 a/d converter user?s manual u17446ej5v0ud 171 (4) 8-bit a/d conversion result register (adcrh) this register is an 8-bit register that stores the a/d conversion result. it stores the higher 8 bits of a 10-bit resolution result. adcrh can be read by an 8-bit memory manipulation instruction. reset signal generation makes adcrh undefined. figure 10-7. format of 8-bit a/d c onversion result register (adcrh) symbol adcrh 76543210 address: ff1ah after reset: undefined r (5) port mode control register 2 (p mc2) and port mode register 2 (pm2) when using the p20/ani0 to p23/ani3 pins for analog in put, set pmc20 to pmc23 and pm20 to pm23 to 1. at this time, the output latches of p20 to p23 may be 0 or 1. pmc2 and pm2 are set by a 1-bit or 8- bit memory manipulation instruction. reset signal generation clears pmc2 to 00h and sets pm2 to ffh. figure 10-8. format of port m ode control register 2 (pmc2) address: ff84h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pmc2 0 0 0 0 pmc23 pmc22 pmc21 pmc20 pmc2n operation mode specification (n = 0 to 3) 0 port mode 1 a/d converter mode caution when pmc20 to pmc23 are set to 1, the p20/ani 0 to p23/ani3 pins cannot be used as port pins. be sure to set the pull-up resistor opt ion registers (pu20 to pu23) to 0 for the pins set to a/d converter mode. figure 10-9. format of port mode register 2 (pm2) address: ff22h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm2 1 1 1 1 pm23 pm22 pm21 pm20 pm2n pmn pin i/o mode selection (n = 0 to 3) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 10 a/d converter user?s manual u17446ej5v0ud 172 10.4 a/d converter operations 10.4.1 basic operations of a/d converter <1> set adce to 1. <2> select one channel for a/d conversion using the an alog input channel specificat ion register (ads), and select the conversion time using fr2 to fr0. <3> execute two nop instructions or an inst ruction equivalent to two machine cycles. <4> set adcs to 1 and start the conversion operation. (<5> to <11> are operations performed by hardware.) <5> the voltage input to the selected analog input c hannel is sampled by the sample & hold circuit. <6> when sampling has been done for a certain time, the sa mple & hold circuit is placed in the hold state and the input analog voltage is held until the a/d conversion operation has ended. <7> bit 9 of the successive approximation register (sar) is set. the d/a converter voltage tap is set to (1/2) av ref by the tap selector. <8> the voltage difference between the d/a converter volt age tap and analog input is compared by the voltage comparator. if the analog input is greater than (1/2) av ref , the msb of sar remains set to 1. if the analog input is smaller than (1/2) av ref , the msb is reset to 0. <9> next, bit 8 of sar is automatically set to 1, and the operation proceeds to t he next comparison. the d/a converter voltage tap is selected according to t he preset value of bit 9, as described below. ? bit 9 = 1: (3/4) av ref ? bit 9 = 0: (1/4) av ref the voltage tap and analog input vo ltage are compared and bit 8 of sar is manipulated as follows. ? analog input voltage voltage tap: bit 8 = 1 ? analog input voltage < voltage tap: bit 8 = 0 <10> comparison is continued in this way up to bit 0 of sar. <11> upon completion of the comparison of 10 bits, an effective digital result value remains in sar, and the result value is transferred to the a/d conversion resu lt register (adcr, adcrh) and then latched. at the same time, the a/d conversion end in terrupt request (intad) can also be generated. <12> repeat steps <5> to <11>, until adcs is cleared to 0. to stop the a/d converter, clear adcs to 0. to restart a/d conversion from the st atus of adce = 1, start from <3>. to restart a/d conversion from the status of adce = 0, however, star t from <1> (when not changing the channel and conversion time, skip step <2>). cautions 1. make sure the period of <1> to <4> is 1 s or more. 2. it is no problem if the or der of <1> and <2> is reversed. remark the following two types of a/d conv ersion result registers can be used. ? adcr (16 bits): stores a 10-bit a/d conversion value. ? adcrh (8 bits): stores an 8-bit a/d conversion value. chapter 10 a/d converter user?s manual u17446ej5v0ud 173 figure 10-10. basic operation of a/d converter conversion time sampling time sampling a/d conversion undefined conversion result a/d converter operation sar adcr, adcrh intad conversion result a/d conversion operations are performed continuously until bit 7 (adcs) of t he a/d converter mode register (adm) is reset (0) by software. if a write operation is performed to adm or the analog in put channel specification r egister (ads) during an a/d conversion operation, the conversion oper ation is initialized, and if the adcs bi t is set (1), conversion starts again from the beginning. reset input makes the a/d conversion resu lt register (adcr, adcrh) undefined. chapter 10 a/d converter user?s manual u17446ej5v0ud 174 10.4.2 input voltage and conversion results the relationship between the analog input voltage input to the analog input pins (ani0 to ani3) and the theoretical a/d conversion result (stored in the 10-bit a/d conver sion result register (adcr)) is shown by the following expression. adcr = int ( 1024 + 0.5) or (adcr ? 0.5) v ain < (adcr + 0.5) where, int( ): function which returns integer part of value in parentheses v ain : analog input voltage av ref : av ref pin voltage adcr: 10-bit a/d conversion result register (adcr) value figure 10-11 shows the relationship between the analo g input voltage and the a/d conversion result. figure 10-11. relationship between analog i nput voltage and a/d conversion result 1023 1022 1021 3 2 1 0 03ffh 03feh 03fdh 0003h 0002h 0001h 0000h a/d conversion result sar adcr 1 2048 1 1024 3 2048 2 1024 5 2048 input voltage/av ref 3 1024 2043 2048 1022 1024 2045 2048 1023 1024 2047 2048 1 v ain av ref av ref 1024 av ref 1024 chapter 10 a/d converter user?s manual u17446ej5v0ud 175 10.4.3 a/d converter operation mode the operation mode of the a/d converter is the select mode. one channe l of analog input is selected from ani0 to ani3 by the analog input channel specification register (ads) and a/d co nversion is executed. (1) a/d conversion operation by setting bit 7 (adcs) of the a/d converter mode regist er (adm) to 1, the a/d conversion operation of the voltage, which is applied to the analog input pin specif ied by the analog input channel specification register (ads), is started. when a/d conversion has been completed, the result of the a/d c onversion is stored in t he a/d conversion result register (adcr, adcrh), and an interrupt request signal (intad) is generated. on ce the a/d conversion has started and when one a/d conversion has been completed, the next a/d c onversion operation is immediately started. the a/d conversion operations are repeated until new data is written to ads. if adm or ads is written during a/d conversion, the a/d conversion operation under execution is stopped and restarted from the beginning. if 0 is written to adcs during a/d conversion, a/d conv ersion is immediately stopped. at this time, the conversion result is undefined. figure 10-12. a/d conversion operation anin rewriting adm adcs = 1 rewriting ads adcs = 0 anin anin anin anim anin anim anim stopped a/d conversion adcr, adcrh intad conversion is stopped conversion result is not retained remarks 1. n = 0 to 3 2. m = 0 to 3 chapter 10 a/d converter user?s manual u17446ej5v0ud 176 the setting method is described below. <1> set bit 0 (adce) of the a/d converter mode register (adm) to 1. <2> select the channel and conversion time using bi ts 1 and 0 (ads1, ads0) of the analog input channel specification register (ads) and bits 5 to 3 (fr2 to fr0) of adm. <3> execute two nop instructions or an in struction equivalent to two machine cycles. <4> set bit 7 (adcs) of adm to 1 to start a/d conversion. <5> an interrupt request signal (intad) is generated. <6> transfer the a/d conversion data to the a/d conversion result register (adcr, adcrh). chapter 10 a/d converter user?s manual u17446ej5v0ud 177 10.5 how to read a/d converter characteristics table here, special terms unique to the a/d converter are explained. (1) resolution this is the minimum analog input vo ltage that can be identif ied. that is, the perce ntage of the analog input voltage per bit of digital output is called 1lsb (least si gnificant bit). the percentage of 1lsb with respect to the full scale is expressed by %fsr (full scale range). 1lsb is as follows when the resolution is 10 bits. 1lsb = 1/2 10 = 1/1024 = 0.098%fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these express the overall error. note that the quantization error is not included in the overall erro r in the characteristics table. (3) quantization error when analog values are converted to digital values, a 1/2lsb error naturally occurs. in an a/d converter, an analog input voltage in a range of 1/2lsb is converted to the same digita l code, so a quantization error cannot be avoided. note that the quantization erro r is not included in the overall error, zero -scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. figure 10-13. overall error figur e 10-14. quanti zation error ideal line 0 ?? 0 1 ?? 1 digital output overall error analog input av ref 0 0 ?? 0 1 ?? 1 digital output quantization error 1/2lsb 1/2lsb analog input 0 av ref (4) zero-scale error this shows the difference between the actual measuremen t value of the analog input vo ltage and the theoretical value (1/2lsb) when the digital output changes from 0......000 to 0......001. if the actual measurement value is greater than the theore tical value, it shows the difference between the actual measurement value of the analog in put voltage and the theoretical val ue (3/2lsb) when the digital output changes from 0??001 to 0??010. chapter 10 a/d converter user?s manual u17446ej5v0ud 178 (5) full-scale error this shows the difference between the actual measuremen t value of the analog input vo ltage and the theoretical value (full-scale ? 3/2lsb) when the digital output chan ges from 1......110 to 1......111. (6) integral linearity error this shows the degree to which the conversion charac teristics deviate from the ideal linear relationship. it expresses the maximum value of the di fference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. (7) differential linearity error while the ideal width of code output is 1lsb, this indi cates the difference between the actual measurement value and the ideal value. figure 10-15. zero-scale error figure 10-16. full-scale error 111 011 010 001 zero-scale error ideal line 000 01 2 3 av ref digital output (lower 3 bits) analog input (lsb) 111 110 101 000 0 av ref ? 3 full-scale error ideal line analog input (lsb) digital output (lower 3 bits) av ref ? 2av ref ? 1 av ref figure 10-17. integral linearity error figure 10-18. differential linearity error 0 av ref digital output analog input integral linearity error ideal line 1 ?? 1 0 ?? 0 0 av ref digital output analog input differential linearity error 1 ?? 1 0 ?? 0 ideal 1lsb width (8) conversion time this expresses the time from the start of samp ling to when the digital output is obtained. the sampling time is included in the conv ersion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on for the anal og voltage to be sampled by the sample & hold circuit. sampling time conversion time chapter 10 a/d converter user?s manual u17446ej5v0ud 179 10.6 cautions for a/d converter (1) operating current in stop mode to satisfy the dc characteristics of the supply current in the stop mode, clear bit 7 (adcs) and bit 0 (adce) of the a/d converter mode register (adm) to 0 before executing the stop instruction. (2) input range of ani0 to ani3 observe the rated range of the ani0 to an i3 input voltage. if a voltage of av ref or higher and av ss or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. in addition, the converted values of the other channels may also be affected. (3) conflicting operations <1> conflict between a/d conversion result regist er (adcr, adcrh) write and adcr, adcrh read by instruction upon the end of conversion adcr, adcrh read has priority. after the read operat ion, the new conversion result is written to adcr, adcrh. <2> conflict between adcr, adcrh writ e and a/d converter mode register (adm) write or analog input channel specification register (ads ) write upon the end of conversion adm or ads write has priority. adcr, adcrh write is not performed, nor is the conversion end interrupt signal (intad) generated. (4) noise countermeasures to maintain the 10-bit resolution, attent ion must be paid to noise input to the av ref pin and pins ani0 to ani3. <1> connect a capacitor with a low equivalent resistanc e and a high frequency response to the power supply. <2> because the effect increases in proportion to t he output impedance of the an alog input source, it is recommended that a capacitor be connected external ly, as shown in figure 10-19, to reduce noise. <3> do not switch the a/d conversion function of the ani0 to ani3 pins to their alternate functions during conversion. <4> the conversion accuracy can be improved by setting ha lt mode immediately after the conversion starts. figure 10-19. analog input pin connection reference voltage input c = 0.01 to 0.1 f if there is a possibility that noise equal to or higher than av ref or equal to or lower than av ss may enter, clamp with a diode with a small v f value (0.3 v or lower). av ref ani0 to ani3 av ss v ss chapter 10 a/d converter user?s manual u17446ej5v0ud 180 (5) ani0/p20 to ani3/p23 <1> the analog input pins (ani0 to ani3) ar e also used as i/o port pins (p20 to p23). when a/d conversion is performed with any of ani0 to ani3 selected, do not access port 2 (p20 to p23) while conversion is in progress; otherwise the conversion resolution may be degraded. <2> if a digital pulse is applied to the pins adjacent to t he pins currently used for a/ d conversion, the expected value of the a/d conversion may not be obtained due to coupling noise. t herefore, do not apply a pulse to the pins adjacent to the pi n undergoing a/d conversion. (6) input impedance of ani0 to ani3 pins in this a/d converter, the internal sampling capacitor is charged and sampling is performed during sampling time. since only the leakage current flows other than during sa mpling and the current for charging the capacitor also flows during sampling, the input impedance fl uctuates both during sa mpling and otherwise. if the shortest conversion time of the reference voltage is used, to perform sufficient sampling, it is recommended to make the output impedance of the analog input source 1 k or lower, or attach a capacitor of around 0.01 f to 0.1 f to the ani0 to ani3 pins (see figure 10-19 ). (7) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if th e analog input channel specification register (ads) is changed. therefore, if an analog input pin is changed during a/d conversion, the a/d conversion result and adif for the pre-change analog input may be set just before the ads rewrit e. caution is therefore re quired since, at this time, when adif is read immediately after the ads rewrite, ad if is set despite the fact a/d conversion for the post- change analog input has not ended. when a/d conversion is stopped and then resumed, clear ad if before the a/d conversion operation is resumed. figure 10-20. timing of a/d conver sion end interrupt request generation ads rewrite (start of anin conversion) a/d conversion adcr, adcrh adif anin anin anim anim anin anin anim anim ads rewrite (start of anim conversion) adif is set but anim conversion has not ended. remarks 1. n = 0 to 3 2. m = 0 to 3 chapter 10 a/d converter user?s manual u17446ej5v0ud 181 (8) conversion results just after a/d conversion start the first a/d conversion value immediately after a/d conv ersion starts may not fall wit hin the rating range if the adcs bit is set to 1 within 1 s after the adce bit was set to 1, or if t he adcs bit is set to 1 with the adce bit = 0. take measures such as pollin g the a/d conversion end interrupt r equest (intad) and removing the first conversion result. (9) a/d conversion result regist er (adcr, adcrh) read operation when a write operation is performed to the a/d conver ter mode register (adm) and analog input channel specification register (ads), t he contents of adcr and adcrh may beco me undefined. read the conversion result following conversion completion before writing to adm and ads. using a timing other than the above may cause an incorrect conversion result to be read. (10) operating current at conversion waiting mode the dc characteristic of the operati ng current during the stop mode is not satisfied due to the conversion waiting mode (only the comparator c onsumes power), when bit 7 (adcs) and bi t 0 (adce) of the a/d converter mode register (adm) are set to 0 and 1 respectively. (11) internal equivalent circuit the equivalent circuit of the analog input block is shown below. figure 10-21. internal equi valent circuit of anin pin anin c out c in r in lsi internal r out table 10-3. resistance and capacitance valu es (reference values) of equivalent circuit av ref r out r in c out c in 4.5 v av ref 5.5 v 1 k 3 k 8 pf 15 pf 2.7 v av ref < 4.5 v 1 k 60 k 8 pf 15 pf remarks 1. the resistance and capacitance values shown in table 10-3 are not guaranteed values. 2. n = 0 to 3 3. r out : allowable signal source impedance r in : analog input equivalent resistance c in : analog input equivalent capacitance c out : internal pin capacitance user?s manual u17446ej5v0ud 182 chapter 11 serial interface uart6 11.1 functions of serial interface uart6 serial interface uart6 has the following two modes. (1) operation stop mode this mode is used when serial communication is not executed and can enable a reduction in the power consumption. for details, see 11.4.1 operation stop mode . (2) asynchronous serial interface (uart) mode this mode supports the lin (local interconnect network) -bus. the functions of this mode are outlined below. for details, see 11.4.2 asynchronous seri al interface (uart) mode and 11.4.3 dedicated baud rate generator . ? two-pin configuration t x d6: transmit data output pin r x d6: receive data input pin ? data length of communication data can be selected from 7 or 8 bits. ? dedicated internal 8-bit baud rate generator allowing any baud rate to be set ? transmission and reception can be performed independently. ? msb- or lsb-first communication selectable ? inverted transmission operation ? synchronous break field transmission from 13 to 20 bits ? more than 11 bits can be identified for synchronous break field reception (sbf reception flag provided). cautions 1. the t x d6 output inversion function inverts only th e transmission side a nd not the reception side. to use this f unction, the reception side must be ready for reception of inverted data. 2. if clock supply to serial interface uart6 is not stopped (e .g., in the halt mode), normal operation continues. if clock supply to serial interface uart6 is stopped (e.g., in the stop mode), each register stops operating, and hold s the value immediatel y before clock supply was stopped. the t x d6 pin also holds the value imme diately before clock supply was stopped and outputs it. however, the operati on is not guaranteed after clock supply is resumed. therefore, reset the circuit so th at power6 = 0, rxe6 = 0, and txe6 = 0. 3. if data is continuously tr ansmitted, the communicat ion timing from the stop bit to the next start bit is extended two operating clocks of the macro. however, th is does not affect the result of communication because the reception side initializ es the timing when it has detected a start bit. do no t use the continuous transmissi on function if the interface is used in lin communication operation. chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 183 remark lin stands for local interconnect network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. lin communication is single-master communication, and up to 15 slaves can be connected to one master. the lin slaves are used to contro l the switches, actuator s, and sensors, and thes e are connected to the lin master via the lin network. normally, the lin master is connected to a network such as can (controller area network). in addition, the lin bus uses a single-wire method and is connected to the nodes via a transceiver that complies with iso9141. in the lin protocol, the master tr ansmits a frame with baud rate information and the slave receives it and corrects the baud rate error. theref ore, communication is possible when the baud rate error in the slave is 15% or less. figures 11-1 and 11-2 outline the transmissi on and reception operations of lin. figure 11-1. lin transmission operation lin bus wakeup signal frame 8 bits note 1 55h transmission data transmission data transmission data transmission data transmission 13-bit note 2 sbf transmission note 3 synchronous break field synchronous field identifier field data field data field checksum field txd6 (output) intst6 notes 1. the wakeup signal frame is substituted by 80h transmission in the 8-bit mode. 2. the synchronous break field is output by hardware. the output width is equal to the bit length set by bits 4 to 2 (sbl62 to sbl60) of asynchronous se rial interface control register 6 (asicl6) (see 11.4.2 (2) (h) sbf transmission ). 3. intst6 is output on completion of each transmissi on. it is also output when sbf is transmitted. remark the interval between each field is controlled by software. chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 184 figure 11-2. lin reception operation lin bus 13 bits sf reception id reception data reception data reception data reception wakeup signal frame synchronous break field synchronous field identifier field data field data field checksum field rxd6 (input) sbf reception reception interrupt (intsr6) edge detection (intp0) capture timer disable enable disable enable <1> <2> <3> <4> <5> <1> the wakeup signal is detected at the edge of the pin, and enables ua rt6 and sets the sbf reception mode. <2> reception continues until the stop bit is detected. when an sbf with low-level data of 11 bits or more has been detected, it is assumed that sbf reception has been completed correctly, and an interrupt request signal is output. if an sbf with low-level data of less than 11 bits has been detected, it is assumed that an sbf reception error has occurred. the interrupt reques t signal is not output and the sbf reception mode is restored. <3> if sbf reception has been completed correctly, an interrupt request signal is output. start the 16-bit timer/event counter 00 during sbf reception completi on interrupt processing, and measure the bit width (pulse width) of the sync field (refer to 6.4.3 pulse width measurement operations ). detection of errors ove6, pe6, and fe6 is suppressed, and error detec tion processing of uart communication and data transfer of the shift register and rxb6 is not perfo rmed. the shift register holds the reset value ffh. <4> calculate the baud rate error from the bit interval of the synchronous field, disable uart6 after sf reception, and then re-set baud rate generator control register 6 (brgc6). <5> distinguish the checksum field by software. also perform processing by software to initialize uart6 after reception of the checksum field and to set the sbf reception mode again. figure 11-3 illustrates the port confi guration for lin reception operation. the wakeup signal transmitted from the lin master is received by detecting the edge of the external interrupt (intp0). the length of the synchronous field transmitted from the lin master can be measured using the external event capture operation of 16-bit ti mer/event counter 00, and the bau d rate error can be calculated. the input signal of the reception port input (rxd6) ca n be input to the external interrupt (intp0) and 16-bit timer/event counter 00 by port input switch control (isc0/isc1), without co nnecting rxd6 and intp0/ti000 externally. chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 185 figure 11-3. port configurati on for lin reception operation rxd6 input intp0 input ti000 input p44/r x d6 p30/intp0/ti000 port input selection control (isc0) chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 186 11.2 configuration of serial interface uart6 serial interface uart6 consis ts of the following hardware. table 11-1. configurati on of serial interface uart6 item configuration registers receive buffer register 6 (rxb6) receive shift register 6 (rxs6) transmit buffer register 6 (txb6) transmit shift register 6 (txs6) control registers asynchronous serial interface o peration mode register 6 (asim6) asynchronous serial interface recepti on error status register 6 (asis6) asynchronous serial interface transm ission status register 6 (asif6) clock selection register 6 (cksr6) baud rate generator control register 6 (brgc6) asynchronous serial interface control register 6 (asicl6) input switch control register (isc) port mode register 4 (pm4) port register 4 (p4) chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 187 figure 11-4. block diagram of serial interface uart6 internal bus asynchronous serial interface control register 6 (asicl6) transmit buffer register 6 (txb6) transmit shift register 6 (txs6) t x d6/ intp1/p43 intst6 baud rate generator asynchronous serial interface control register 6 (asicl6) reception control receive shift register 6 (rxs6) receive buffer register 6 (rxb6) r x d6/ p44 ti000, intp0 note intsr6 baud rate generator filter intsre6 asynchronous serial interface reception error status register 6 (asis6) asynchronous serial interface operation mode register 6 (asim6) asynchronous serial interface transmission status register 6 (asif6) transmission control registers f xp f xp /2 f xp /2 2 f xp /2 3 f xp /2 4 f xp /2 5 f xp /2 6 f xp /2 7 f xp /2 8 f xp /2 9 f xp /2 10 f xp /2 11 8 reception unit transmission unit clock selection register 6 (cksr6) baud rate generator control register 6 (brgc6) output latch (p43) pm43 8 selector f xclk6 (base clock) note selectable with input switch control register (isc). chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 188 (1) receive buffer register 6 (rxb6) this 8-bit register stores parallel data conv erted by receive shift register 6 (rxs6). each time 1 byte of data has been received, new receive dat a is transferred to this r egister from receive shift register 6 (rxs6). if the data length is set to 7 bits, data is transferred as follows. ? in lsb-first reception, the receive data is transferred to bits 0 to 6 of rxb6 and the msb of rxb6 is always 0. ? in msb-first reception, the receive data is transferred to bits 7 to 1 of rxb6 and the lsb of rxb6 is always 0. if an overrun error (ove6) occurs, the rece ive data is not transferred to rxb6. rxb6 can be read by an 8-bit memory manipulation inst ruction. no data can be written to this register. generation of reset signal sets this register to ffh. caution reception enable status is entered, after having set rxe6 to 1 and one clock of the base clock (f xclk6 ) has elapsed. (2) receive shift register 6 (rxs6) this register converts the serial data input to the r x d6 pin into parallel data. rxs6 cannot be directly manipulated by a program. (3) transmit buffer register 6 (txb6) this buffer register is used to set transmit data. tr ansmission is started when data is written to txb6. if the data length is set to 7 bits: ? in lsb-fast transmission, data is transferred to bits 0 to 6 of txb6, and the msb of txb6 is not transmitted. ? in msb-fast transmission, data is transferred to bits 7 to 1 of txb6, and the lsb of txb6 is not transmitted. this register can be read or written by an 8-bit memory manipulation instruction. generation of reset signal sets this register to ffh. cautions 1. when starting transmi ssion, write transmit data to txb6, after having set txe6 to 1 and a wait of one clock or more of the base clock (f xclk6 ) has been performed. 2. do not write data to txb6 when bit 1 (txbf6) of asynchronous serial interface transmission status register 6 (asif6) is 1. 3. do not refresh (write the same value to) txb6 by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asynchr onous serial interface operation mode register 6 (asim6) are 1 or when bit 7 (power6) and bit 5 (rxe6) of asim6 are 1). when outputting same values in continuous transmission, be su re to confirm that txbf6 is 0 before writing the same values to txb6. (4) transmit shift register 6 (txs6) this register transmits the data transferred from txb6 from the t x d6 pin as serial data. data is transferred from txb6 immediately after txb6 is written for the first tr ansmission, or immediately before intst6 occurs after one frame was transmitted for continuous transmission. da ta is transferred from txb6 and transmitted from the t x d6 pin at the falling edge of the base clock. txs6 cannot be directly manipulated by a program. chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 189 11.3 registers controlling serial interface uart6 serial interface uart6 is controlle d by the following nine registers. ? asynchronous serial interface operation mode register 6 (asim6) ? asynchronous serial interface recept ion error status register 6 (asis6) ? asynchronous serial interface transmission status register 6 (asif6) ? clock selection register 6 (cksr6) ? baud rate generator control register 6 (brgc6) ? asynchronous serial interface control register 6 (asicl6) ? input switch control register (isc) ? port mode register 4 (pm4) ? port register 4 (p4) (1) asynchronous serial interface ope ration mode register 6 (asim6) this 8-bit register controls the serial comm unication operations of serial interface uart6. this register can be set by a 1-bit or 8-bit memory manipulation instruction. generation of reset signal sets this register to 01h. remark asim6 can be refreshed (the same value is wr itten) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). figure 11-5. format of asynchronous serial inte rface operation mode register 6 (asim6) (1/2) address: ff90h after reset: 01h r/w symbol <7> <6> <5> 4 3 2 1 0 asim6 power6 txe6 rxe6 ps61 ps60 cl6 sl6 isrm6 power6 enabling/disabling operat ion of internal operation clock 0 note 1 disable operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit note 2 . 1 note 3 enable operation of the internal operation clock notes 1. the output of the t x d6 pin goes high and the input from the r x d6 pin is fixed to the high level when power6 is cleared to 0 during a transmission 0. 2. asynchronous serial interface reception error status register 6 (asis6), asynchronous serial interface transmission status register 6 (asif6), bit 7 ( sbrf6) and bit 6 (sbrt6) of asynchronous serial interface control register 6 (asicl6), and receive buffer register 6 (rxb6) are reset. 3. a base clock (f xclk6 ) is supplied as the internal operation cl ock when the power6 bit is set to 1 and one clock of the base clock (f xclk6 ) has elapsed. chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 190 figure 11-5. format of asynchronous serial inte rface operation mode register 6 (asim6) (2/2) txe6 note 1 enabling/disabling transmission 0 disable transmission (synchronously reset the transmission circuit). 1 enable transmission rxe6 note 2 enabling/disabling reception 0 disable reception (synchronous ly reset the reception circuit). 1 enable reception ps61 ps60 transmission oper ation reception operation 0 0 parity bit not output. reception without parity 0 1 output 0 parity. reception as 0 parity note 3 1 0 output odd parity. judge as odd parity. 1 1 output even parity. judge as even parity. cl6 specification of character length of transmit/receive data 0 character length of data = 7 bits 1 character length of data = 8 bits sl6 specification of number of stop bits of transmit data 0 number of stop bits = 1 1 number of stop bits = 2 isrm6 enabling/disabling occurrence of recept ion completion interrupt in case of error 0 ?intsre6? occurs in case of error (at this time, intsr6 does not occur). 1 ?intsr6? occurs in case of error (at this time, intsre6 does not occur). notes 1. txe6 is synchronized by the base clock (f xclk6 ) set by cksr6. when re-enabling transmission operation, set txe6 to 1 after having set txe6 to 0 and one clock of the base clock (f xclk6 ) has elapsed. if txe6 is set to 1 before one clock of the base clock (f xclk6 ) has elapsed, the transmission circuit may not able to be initialized. 2. rxe6 is synchronized by the base clock (f xclk6 ) set by cksr6. when re-enabling reception operation, set rxe6 to 1 after having set rxe6 to 0 and one clock of the base clock (f xclk6 ) has elapsed. if rxe6 is set to 1 before one clock of the base clock (f xclk6 ) has elapsed, the reception circuit may not be able to be initialized. 3. if ?reception as 0 parity? is sele cted, the parity is not judged. ther efore, bit 2 (pe6) of asynchronous serial interface reception error status register 6 (asis6) is not set and the error interrupt does not occur. caution 1. at startup, transmission operation is star ted by setting txe6 to 1 after having set power6 to 1, then setting the transmit data to txb6 afte r having waited for one clock or more of the base clock (f xclk6 ). when stopping transmission operation, set power6 to 0 after having set txe6 to 0. chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 191 cautions 2. at startup, reception en able status is entered after havi ng set power6 to 1, then setting rxe6 to 1, and one cl ock of the base clock (f xclk6 ) has elapsed. when stopping reception operation, set power6 to 0 a fter having set rxe6 to 0. 3. set power6 = 1 rxe6 = 1 in a state where a high level has been input to the rxd6 pin. if power6 = 1 rxe6 = 1 is set during low-level input, reception is started and correct data will not be received. 4. clear the txe6 and rxe6 bits to 0 be fore rewriting the ps61, ps60, and cl6 bits. 5. fix the ps61 and ps60 bits to 0 when the interface is used in lin communication operation. 6. make sure that txe6 = 0 wh en rewriting the sl6 bit. recep tion is always performed with ?the number of stop bits = 1?, and therefore, is not affected by the set value of the sl6 bit. 7. make sure that rxe6 = 0 when rewriting the isrm6 bit. (2) asynchronous serial interface recepti on error status register 6 (asis6) this register indicates an error status on completion of re ception by serial interface uart6. it includes three error flag bits (pe6, fe6, ove6). this register is read-only by an 8-bit memory manipulation instruction. reset signal generation clears this regist er to 00h if bit 7 (power6) and bit 5 (rxe6) of asim6 = 0. 00h is read when this register is read. figure 11-6. format of asynchronous serial inte rface reception error status register 6 (asis6) address: ff93h after reset: 00h r symbol 7 6 5 4 3 2 1 0 asis6 0 0 0 0 0 pe6 fe6 ove6 pe6 status flag indicating parity error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if the parity of transmit data does not match the parity bit on completion of reception fe6 status flag indicating framing error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if the stop bit is not detected on completion of reception ove6 status flag indicating overrun error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if receive data is set to the rxb register and the next reception operation is completed before the data is read. cautions 1. the operation of the pe6 bit differs depending on the set values of the ps61 and ps60 bits of asynchronous serial interface operati on mode register 6 (asim6). 2. the first bit of the receive da ta is checked as the stop bit, regardless of the number of stop bits. 3. if an overrun error occurs , the next receive data is not wr itten to receive buffer register 6 (rxb6) but discarded. 4. be sure to read asis6 before r eading receive buffer register 6 (rxb6). chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 192 (3) asynchronous serial interface tran smission status register 6 (asif6) this register indicates the status of transmission by se rial interface uart6. it includes two status flag bits (txbf6 and txsf6). transmission can be continued without disruption even during an interrupt period, by writing the next data to the txb6 register after data has been transferred from the txb6 register to the txs6 register. this register is read-only by an 8-bit memory manipulation instruction. reset signal generation clears this register to 00h if bit 7 (power6) and bit 6 (txe6) of asim6 = 0. figure 11-7. format of asynchronous serial in terface transmission status register 6 (asif6) address: ff95h after reset: 00h r symbol 7 6 5 4 3 2 1 0 asif6 0 0 0 0 0 0 txbf6 txsf6 txbf6 transmit buffer data flag 0 if power6 = 0 or txe6 = 0, or if data is tr ansferred to transmit shift register 6 (txs6) 1 if data is written to transmit buffer register 6 (txb6) (if data exists in txb6) txsf6 transmit shift register data flag 0 if power6 = 0 or txe6 = 0, or if the next data is not transferred from transmit buffer register 6 (txb6) after completion of transfer 1 if data is transferred from transmit buffer regist er 6 (txb6) (if data transmi ssion is in progress) cautions 1. to transmit data conti nuously, write the first transmit data (first byte) to the txb6 register. be sure to check that the txbf6 fl ag is ?0?. if so, write the next transmit data (second byte) to the txb6 register. if data is written to th e txb6 register while the txbf6 flag is ?1?, the transmit data cannot be guaranteed. 2. to initialize the transmission unit upon comple tion of continuous transmission, be sure to check that the txsf6 flag is ?0 ? after generation of the tran smission completion interrupt, and then execute initializat ion. if initiali zation is executed while the txsf6 flag is ?1?, the transmit data cannot be guaranteed. chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 193 (4) clock selection register 6 (cksr6) this register selects the base cl ock of serial interface uart6. cksr6 can be set by an 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. remark cksr6 can be refreshed (the same value is wr itten) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). figure 11-8. format of clock selection register 6 (cksr6) address: ff96h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 cksr6 0 0 0 0 tps63 tps62 tps61 tps60 tps63 tps62 tps61 tps60 base clock (f xclk6 ) selection 0 0 0 0 f xp (10 mhz) 0 0 0 1 f xp /2 (5 mhz) 0 0 1 0 f xp /2 2 (2.5 mhz) 0 0 1 1 f xp /2 3 (1.25 mhz) 0 1 0 0 f xp /2 4 (625 khz) 0 1 0 1 f xp /2 5 (312.5 khz) 0 1 1 0 f xp /2 6 (156.25 khz) 0 1 1 1 f xp /2 7 (78.13 khz) 1 0 0 0 f xp /2 8 (39.06 khz) 1 0 0 1 f xp /2 9 (19.53 khz) 1 0 1 0 f xp /2 10 (9.77 khz) 1 0 1 1 f xp /2 11 (4.89 khz) other than above setting prohibited caution make sure power6 = 0 wh en rewriting tps63 to tps60. remarks 1. figures in parentheses are for operation with f xp = 10 mhz 2. f xp : oscillation frequency of clock to peripheral hardware chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 194 (5) baud rate generator c ontrol register 6 (brgc6) this register sets the division value of t he 8-bit counter of serial interface uart6. brgc6 can be set by an 8-bit memory manipulation instruction. generation of reset signal sets this register to ffh. remark brgc6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). figure 11-9. format of baud rate ge nerator control register 6 (brgc6) address: ff97h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 brgc6 mdl67 mdl66 mdl65 mdl64 mdl63 mdl62 mdl61 mdl60 mdl67 mdl66 mdl65 mdl64 mdl63 mdl62 mdl61 mdl60 k output clock selection of 8-bit counter 0 0 0 0 0 setting prohibited 0 0 0 0 1 0 0 0 8 f xclk6 /8 0 0 0 0 1 0 0 1 9 f xclk6 /9 0 0 0 0 1 0 1 0 10 f xclk6 /10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 1 1 1 0 0 252 f xclk6 /252 1 1 1 1 1 1 0 1 253 f xclk6 /253 1 1 1 1 1 1 1 0 254 f xclk6 /254 1 1 1 1 1 1 1 1 255 f xclk6 /255 cautions 1. make sure that bit 6 (txe6) and bit 5 (rxe6) of the asim6 register = 0 when rewriting the mdl67 to mdl60 bits. 2. the baud rate is the output clo ck of the 8-bit counter divided by 2. remarks 1. f xclk6 : frequency of base clock selected by the t ps63 to tps60 bits of cksr6 register 2. k: value set by mdl67 to mdl60 bits (k = 8, 9, 10, ..., 255) 3. : don?t care chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 195 (6) asynchronous serial interface control register 6 (asicl6) this register controls the serial communicati on operations of serial interface uart6. asicl6 can be set by a 1-bit or 8-bit memory manipulation instruction. generation of reset signal sets this register to 16h. caution asicl6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 are 1 or when bit 7 (power6) and bit 5 (rxe6) of asim6 are 1), if 0 data has been written to asicl6 by sbrt6 and sbtt6. figure 11-10. format of asynchronous serial interface control register 6 (asicl6) (1/2) address: ff98h after reset: 16h r/w note symbol <7> <6> 5 4 3 2 1 0 asicl6 sbrf6 sbrt6 sbtt6 sbl62 sbl61 sbl60 dir6 txdlv6 sbrf6 sbf reception status flag 0 if power6 = 0 and rxe6 = 0 or if sbf reception has been completed correctly 1 sbf reception in progress sbrt6 sbf reception trigger 0 ? 1 sbf reception trigger sbtt6 sbf transmission trigger 0 ? 1 sbf transmission trigger note bit 7 is read-only. chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 196 figure 11-10. format of asynchronous serial interface control register 6 (asicl6) (2/2) sbl62 sbl61 sbl60 sbf transmission output width control 1 0 1 sbf is output with 13-bit length. 1 1 0 sbf is output with 14-bit length. 1 1 1 sbf is output with 15-bit length. 0 0 0 sbf is output with 16-bit length. 0 0 1 sbf is output with 17-bit length. 0 1 0 sbf is output with 18-bit length. 0 1 1 sbf is output with 19-bit length. 1 0 0 sbf is output with 20-bit length. dir6 specification of first bit 0 msb 1 lsb txdlv6 enabling/disabling inverting t x d6 output 0 normal output of t x d6 1 inverted output of t x d6 cautions 1. in the case of an sbf r eception error, return to sbf recepti on mode again. the status of the sbrf6 flag will be held (1). for details on sbf reception refer to (2) ? (i) sbf reception in 11.4.2 asynchronous serial interface (uart) mode described later. 2. before setting the sbrt6 bit to 1, make sure that bit 7 (power6) and bit 5 (rxe6) of asim6 = 1. moreover, after setting the s brt6 bit to 1, do not clear the sbrt6 bit to 0 before the sbf reception ends (an interrupt request signal is generated). 3. the read value of the sbrt6 bit is always 0. sbrt6 is auto matically cleared to 0 after sbf reception has been co rrectly completed. 4. before setting the sbtt6 bit to 1, make sure that bit 7 (pow er6) and bit 6 (txe6) of asim6 = 1. moreover, after setting the sbtt6 bit to 1, do not clear the sbtt6 bit to 0 before the sbf transmission ends (an interrupt request signal is generated). 5. the read value of the sbtt6 bit is always 0. sbtt6 is automatically clear ed to 0 at the end of sbf transmission. 6. before rewriting the dir6 and txdlv6 bits, clear the txe6 a nd rxe6 bits to 0. chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 197 (7) input switch control register (isc) the input switch control regi ster (isc) is used to receive a status si gnal transmitted from the master during lin (local interconnect network) reception. by setting 1 to isc0 and isc1, the input source to in tp0 and ti000 switches to t he input signal from the p44/rxd6 pin. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 11-11. format of input s witch control register (isc) address: ff8ch after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 isc 0 0 0 0 0 0 isc1 isc0 isc1 ti000 input source selection 0 ti000 (p30) 1 rxd6 (p44) isc0 intp0 input source selection 0 intp0 (p30) 1 rxd6 (p44) (8) port mode register 4 (pm4) this register sets port 4 input/output in 1-bit units. when using the p43/txd6/intp1 pin for serial interface da ta output, clear pm43 to 0 and set the output latch of p43 to 1. when using the p44/rxd6 pin for serial interface data input, set pm44 to 1. the output la tch of p44 at this time may be 0 or 1. pm4 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. figure 11-12. format of port mode register 4 (pm4) address: ff24h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm4 pm47 pm46 pm45 pm44 pm43 pm42 pm41 pm40 pm4n p4n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 198 11.4 operation of serial interface uart6 serial interface uart6 has the following two modes. ? operation stop mode ? asynchronous serial interface (uart) mode 11.4.1 operation stop mode in this mode, serial communication cannot be executed; theref ore, the power consumption can be reduced. in addition, the pins can be used as ordinary po rt pins in this mode. to set the operation stop mode, clear bits 7, 6, and 5 (power6, txe6, and rxe6) of asim6 to 0. (1) register used the operation stop mode is set by asynchronous serial interface operation mode register 6 (asim6). asim6 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 01h. address: ff90h after reset: 01h r/w symbol <7> <6> <5> 4 3 2 1 0 asim6 power6 txe6 rxe6 ps61 ps60 cl6 sl6 isrm6 power6 enabling/disabling operat ion of internal operation clock 0 note 1 disable operation of the internal operation clock (fix the clock to low level) and asynchronously reset the internal circuit note 2 . txe6 enabling/disabling transmission 0 disable transmission operat ion (synchronously reset the transmission circuit). rxe6 enabling/disabling reception 0 disable reception (synchronous ly reset the reception circuit). notes 1. the output of the t x d6 pin goes high and the input from the r x d6 pin is fixed to high level when power6 = 0 during a transmission. 2. asynchronous serial interface reception error status register 6 (asis6), asynchronous serial interface transmission status register 6 (asif6), bit 7 ( sbrf6) and bit 6 (sbrt6) of asynchronous serial interface control register 6 (asicl6), and receive buffer register 6 (rxb6) are reset. caution clear power6 to 0 after clearing txe6 and rxe6 to 0 to set the operation stop mode. to start the operation, set power6 to 1, and then set txe6 and rxe6 to 1. remark to use the rxd6/p44 and txd6/intp1/p43 pins as general-purpose port pins, see chapter 4 port functions . chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 199 11.4.2 asynchronous serial interface (uart) mode in this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. a dedicated uart baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) registers used ? asynchronous serial interface operation mode register 6 (asim6) ? asynchronous serial interface recept ion error status register 6 (asis6) ? asynchronous serial interface transmission status register 6 (asif6) ? clock selection register 6 (cksr6) ? baud rate generator control register 6 (brgc6) ? asynchronous serial interface control register 6 (asicl6) ? input switch control register (isc) ? port mode register 4 (pm4) ? port register 4 (p4) the basic procedure of setting an operatio n in the uart mode is as follows. <1> set the cksr6 register (see figure 11-8 ). <2> set the brgc6 register (see figure 11-9 ). <3> set bits 0 to 4 (isrm6, sl6, cl6, ps60, ps61) of the asim6 register (see figure 11-5 ). <4> set bits 0 and 1 (txdlv6, di r6) of the asicl6 register (see figure 11-10 ). <5> set bit 7 (power6) of the asim6 register to 1. <6> set bit 6 (txe6) of the asim6 register to 1. transmission is enabled. set bit 5 (rxe6) of the asim6 register to 1. reception is enabled. <7> write data to transmit buffer register 6 (txb6). data transmission is started. caution take the relationship with the other party of communication into consideration when setting the port mode register and port regi ster. in order to avoid the ge neration of unintended start bits (falling signals), set pm43 to 0 (output) after having set p43 to 1. chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 200 the relationship between the register settings and pins is shown below. table 11-2. relationship between register settings and pins pin function power6 txe6 rxe6 pm43 p43 pm44 p44 uart6 operation txd6/intp1/p43 rxd6/p44 0 0 0 note note note note stop p43 p44 0 1 note note 1 reception p43 rxd6 1 0 0 1 note note transmission txd6 p44 1 1 1 0 1 1 transmission/ reception txd6 rxd6 note can be set as port function. remark : don?t care power6: bit 7 of asynchronous serial interface operation mode register 6 (asim6) txe6: bit 6 of asim6 rxe6: bit 5 of asim6 pm4: port mode register p4: port output latch chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 201 (2) communication operation (a) format and waveform example of normal transmit/receive data figures 11-13 and 11-14 show the format and waveform example of the normal transmit/receive data. figure 11-13. format of normal uart transmit/receive data 1. lsb-first transmission/reception start bit parity bit d0 d1 d2 d3 d4 1 data frame character bits d5 d6 d7 stop bit 2. msb-first transmission/reception start bit parity bit d7 d6 d5 d4 d3 1 data frame character bits d2 d1 d0 stop bit one data frame consists of the following bits. ? start bit ... 1 bit ? character bits ... 7 or 8 bits ? parity bit ... even parity, odd parity, 0 parity, or no parity ? stop bit ... 1 or 2 bits the character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 6 (asim6). whether data is communicated with the lsb or msb first is specified by bit 1 (dir6) of asynchronous serial interface control register 6 (asicl6). whether the t x d6 pin outputs normal or inverted data is s pecified by bit 0 (txdlv6) of asicl6. chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 202 figure 11-14. example of normal uart transmit/receive data waveform 1. data length: 8 bits, lsb first, parity: even parity, stop bit: 1 bit, communication data: 55h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 parity stop 2. data length: 8 bits, msb first, parity: even parity, stop bit: 1 bit, communication data: 55h 1 data frame start d7 d6 d5 d4 d3 d2 d1 d0 parity stop 3. data length: 8 bits, msb first, parity: even parity, stop bit: 1 bit, communication data: 55h, t x d6 pin inverted output 1 data frame start d7 d6 d5 d4 d3 d2 d1 d0 parity stop 4. data length: 7 bits, lsb first, parity: o dd parity, stop bit: 2 bits, communication data: 36h 1 data frame start d0 d1 d2 d3 d4 d5 d6 parity stop stop 5. data length: 8 bits, lsb first, parity: none, stop bit: 1 bit, communication data: 87h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 stop chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 203 (b) parity types and operation the parity bit is used to detect a bit error in communicati on data. usually, the same type of parity bit is used on both the transmission and reception sides. with even parity and odd parity, a 1-bit (odd number) error can be detected. with zero parity and no parity, an error cannot be detected. caution fix the ps61 and ps60 bits to 0 when the interface is used in lin communication operation. (i) even parity ? transmission transmit data, including the parity bit, is controlled so that the number of bits that are ?1? is even. the value of the parity bit is as follows. if transmit data has an odd number of bits that are ?1?: 1 if transmit data has an even number of bits that are ?1?: 0 ? reception the number of bits that are ?1? in the receive dat a, including the parity bit, is counted. if it is odd, a parity error occurs. (ii) odd parity ? transmission unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are ?1? is odd. if transmit data has an odd number of bits that are ?1?: 0 if transmit data has an even number of bits that are ?1?: 1 ? reception the number of bits that are ?1? in the receive data, including the parit y bit, is counted. if it is even, a parity error occurs. (iii) 0 parity the parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. the parity bit is not detected when the data is received. therefore, a parity error does not occur regardless of whether the parity bit is ?0? or ?1?. (iv) no parity no parity bit is appended to the transmit data. reception is performed assuming t hat there is no parity bit when data is received. because there is no parity bit, a parity error does not occur. chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 204 (c) normal transmission when bit 7 (power6) of asynchronous serial interface o peration mode register 6 (asim6) is set to 1, and then bit 6 (txe6) of asim6 is set to 1 after one clock of the base clock (f xclk6 ) has elapsed, transmission enable status is entered. transmission can be started by writing transmit data to transmit buffer register 6 (txb6). the start bit, parity bit, and stop bi t are automatically appended to the data. when transmission is started, the data in txb6 is transferred to transmit sh ift register 6 (txs6). after that, the data is sequentially out put from txs6 to the t x d6 pin. when transmission is completed, the parity and stop bits set by asim6 are appended and a transmission co mpletion interrupt reques t (intst6) is generated. transmission is stopped until the data to be transmitted next is written to txb6. figure 11-15 shows the timing of the transmission comp letion interrupt request (intst6). this interrupt occurs as soon as the last stop bit has been output. figure 11-15. normal transmission comp letion interrupt request timing 1. stop bit length: 1 intst6 d0 start d1 d2 d6 d7 stop t x d6 (output) parity 2. stop bit length: 2 t x d6 (output) intst6 d0 start d1 d2 d6 d7 parity stop chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 205 (d) continuous transmission the next transmit data can be written to transmit buffer re gister 6 (txb6) as soon as transmit shift register 6 (txs6) has started its shift operation. consequently, even while the intst6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized. in addition, the next transmit data can be written to the txb6 regist er without having to wait for the transmission time of one data frame, by confi rming bit 0 (txsf6) of asynchronous serial interface transmission status register 6 (asif6) after a transmission completion interrupt has occurred. to transmit data continuously, be sure to reference t he asif6 register to check the transmission status and whether the txb6 register can be written, and then write the data. for the continuous transmission procedure, refer to figure 11-16 example of continuous transmission processing flow . cautions 1. use the value of the txbf6 flag to judge whether continuous transmission is possible. do not write the next transmit data, by making a judgment only by the fact that the txsf6 flag has b een set to 1. 2. when the interface is used in lin communication operation, the continuous transmission function cannot be used. m ake sure that asynchronous serial interface transmission status register 6 (asif6) is 00h before writing transmit data to transmit buffer register 6 (txb6). txbf6 writing to txb6 register 0 writing enabled 1 writing disabled caution to transmit data continuously, write the first transmit data (fi rst byte) to the txb6 register. be sure to check that the txbf6 fl ag is ?0?. if so, write the next transmit da ta (second byte) to the txb6 register. if data is written to the txb6 register while the txbf6 flag is ?1?, the transmit data cannot be guaranteed. the communication status can be checked using the txsf6 flag. txsf6 transmission status 0 transmission is completed. 1 transmission is in progress. caution to initialize the transmission unit upon comp letion of continuous transmission, be sure to check that the txsf6 flag is ?0? after generation of the transmission completion interrupt, and then execute initialization. if initializati on is executed while the txsf6 flag is ?1?, the transmit data cannot be guaranteed. chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 206 figure 11-16 shows an example of the continuous transmission processing flow. figure 11-16. example of contin uous transmission processing flow write txb6. set registers. write txb6. transfer executed necessary number of times? yes read asif6 txbf6 = 0? no no yes transmission completion interrupt occurred? read asif6 txsf6 = 0? no no no yes yes yes yes completion of transmission processing transfer executed necessary number of times? remark txb6: transmit buffer register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 (transmit buffer data flag) txsf6: bit 0 of asif6 (trans mit shift register data flag) chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 207 figure 11-17 shows the timing of starting continuous transmission, and figure 11-18 shows the timing of ending continuous transmission. figure 11-17. timing of starting continuous transmission t x d6 start intst6 data (1) data (1) data (2) data (3) data (2) data (1) data (3) ff ff parity stop data (2) parity stop txb6 txs6 txbf6 txsf6 start start note note when asif6 is read, there is a period in which t xbf6 and txsf6 = 1, 1. therefore, judge whether writing is enabled using only the txbf6 bit. remark t x d6: t x d6 pin (output) intst6: interrupt request signal txb6: transmit buffer register 6 txs6: transmit shift register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 txsf6: bit 0 of asif6 chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 208 figure 11-18. timing of ending continuous transmission t x d6 start intst6 data (n ? 1) data (n ? 1) data (n) data (n) data (n ? 1) ff parity stop stop data (n) parity stop txb6 txs6 txbf6 txsf6 power6 or txe6 start remark t x d6: t x d6 pin (output) intst6: interrupt request signal txb6: transmit buffer register 6 txs6: transmit shift register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 txsf6: bit 0 of asif6 power6: bit 7 of asynchronous serial interface operation mode register (asim6) txe6: bit 6 of asynchronous serial interface operation mode register (asim6) chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 209 (e) normal reception reception is enabled and the r x d6 pin input is sampled when bit 7 (power6) of asynchronous serial interface operation mode register 6 (asim6) is set to 1 and then bit 5 (rxe6) of asim6 is set to 1. the 8-bit counter of the baud rate generator st arts counting when the falling edge of the r x d6 pin input is detected. when the set value of baud rate generator control register 6 (brgc6) has been counted, the r x d6 pin input is sampled again ( in figure 11-19). if the r x d6 pin is low level at this time, it is recognized as a start bit. when the start bit is detected, receptio n is started, and serial data is sequ entially stored in the receive shift register (rxs6) at the set baud rate. when the stop bi t has been received, the reception completion interrupt (intsr6) is generated and the data of rxs6 is written to receive buffer register 6 (rxb6). if an overrun error (ove6) occurs, however, the receiv e data is not written to rxb6. even if a parity error (pe6) occurs while reception is in progress, reception continues to the reception position of the stop bit, and an error interrupt (intsr6 /intsre6) is generated on completion of reception. figure 11-19. reception completi on interrupt request timing r x d6 (input) intsr6 start d0 d1 d2 d3 d4 d5 d6 d7 parity rxb6 stop cautions 1. be sure to read receive buffer register 6 (rxb6) e ven if a reception error occurs. otherwise, an overrun error wil l occur when the next data is received, and the reception error status will persist. 2. reception is always performed with the ?num ber of stop bits = 1? . the second stop bit is ignored. 3. be sure to read asynchro nous serial interface reception e rror status register 6 (asis6) before reading rxb6. chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 210 (f) reception error three types of errors may occur during reception: a parity error, framing error, or ov errun error. if the error flag of asynchronous serial interface reception error st atus register 6 (asis6) is set as a result of data reception, a reception error interrupt r equest (intsr6/intsre6) is generated. which error has occurred during reception can be identifi ed by reading the contents of asis6 in the reception error interrupt servicing (intsr6/intsre6) (see figure 11-6 ). the contents of asis6 are reset to 0 when asis6 is read. table 11-3. cause of reception error reception error cause parity error the parity specifi ed for transmission does not match the parity of the receive data. framing error stop bit is not detected. overrun error reception of the next data is completed before data is read from receive buffer register 6 (rxb6). the error interrupt can be separated into reception completion interrupt (intsr6) and error interrupt (intsre6) by clearing bit 0 (isrm6) of asynchronous se rial interface operation mode register 6 (asim6) to 0. figure 11-20. reception error interrupt 1. if isrm6 is cleared to 0 (recep tion completion interr upt (intsr6) and error interrupt (intsre6) are separated) (a) no error during recepti on (b) error during reception intsr6 intsre6 intsr6 intsre6 2. if isrm6 is set to 1 (error interrupt is included in intsr6) (a) no error during recepti on (b) error during reception intsre6 intsr6 intsre6 intsr6 chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 211 (g) noise filter of receive data the r x d6 signal is sampled with the base clock (f xclk6 ) output by the prescaler block. if two sampled values are the same, the output of t he match detector changes, and the data is sampled as input data. because the circuit is configured as shown in figure 11- 21, the internal processing of the reception operation is delayed by two clocks from the external signal status. figure 11-21. noise filter circuit internal signal b internal signal a match detector in base clock r x d6/p44 q in ld_en q (h) sbf transmission when the interface is used in lin communication operation, the sbf (synchronous break field) transmission control function is used for transmissi on. for the transmission operation of lin, see figure 11- 1 lin transmission operation . when bit 7 (power6) of asynchronous serial interface mode register 6 (asim6) is set to 1, the txd6 pin outputs high level. next, when bit 6 (txe6) of asim6 is set to 1, the transmission enabled status is entered, and sbf transmission is started by setting bit 5 (sbtt6) of asynchronous serial interface control register 6 (asicl6) to 1. thereafter, a low level of bits 13 to 20 (set by bits 4 to 2 (sbl62 to sbl60) of asicl6) is output. following the end of sbf transmission, the transmission completi on interrupt request (i ntst6) is generated and sbtt6 is automatically cleared. thereafter, the normal transmission mode is restored. transmission is suspended until the dat a to be transmitted next is written to transmit buffer register 6 (txb6), or until sbtt6 is set to 1. figure 11-22. sbf transmission t x d6 intst6 1 2 3 4 5 6 7 8 9 10 11 12 13 stop sbtt6 remark t x d6: t x d6 pin (output) intst6: transmission completion interrupt request sbtt6: bit 5 of asynchronous serial interface control register 6 (asicl6) chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 212 (i) sbf reception when the interface is used in lin communication oper ation, the sbf (synchronous break field) reception control function is used for reception. for the reception oper ation of lin, see figure 11-2 lin reception operation . reception is enabled when bit 7 (power6) of asynch ronous serial interface operation mode register 6 (asim6) is set to 1 and then bit 5 (rxe6) of asim6 is se t to 1. sbf reception is enabled when bit 6 (sbrt6) of asynchronous serial interface contro l register 6 (asicl6) is set to 1. in the sbf reception enabled status, the r x d6 pin is sampled and the start bit is detected in the same manner as the normal reception enable status. when the start bit has been detected, reception is started, and serial data is sequentially stored in the receive shift register 6 (rxs6) at the set baud rate. w hen the stop bit is received and if the width of sbf is 11 bits or more, a reception completion interrupt reques t (intsr6) is generated as normal processing. at this time, the sbrf6 and sbrt6 bits are automatical ly cleared, and sbf reception ends. detection of errors, such as ove6, pe6, and fe6 (bits 0 to 2 of as ynchronous serial interface reception error status register 6 (asis6)) is suppressed, and error detection processing of uart communication is not performed. in addition, data transfer between receive shift register 6 (rxs6) and receive buffer register 6 (rxb6) is not performed, and the reset value of ffh is retained. if the width of sbf is 10 bits or less, an interrupt does not occur as error processing after the stop bit has been re ceived, and the sbf reception mode is restored. in this case, the sbrf6 and sbrt6 bits are not cleared. figure 11-23. sbf reception 1. normal sbf reception (stop bit is detect ed with a width of more than 10.5 bits) r x d6 sbrt6 /sbrf6 intsr6 12345678910 2. sbf reception error (stop bit is detect ed with a width of 10.5 bits or less) r x d6 sbrt6 /sbrf6 intsr6 12345678910 ? 0 ? remark r x d6: r x d6 pin (input) sbrt6: bit 6 of asynchronous serial interface control register 6 (asicl6) sbrf6: bit 7 of asicl6 intsr6: reception completion interrupt request chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 213 11.4.3 dedicated baud rate generator the dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of uart6. separate 8-bit counters are provided for transmission and reception. (1) configuration of ba ud rate generator ? base clock the clock selected by bits 3 to 0 (tps63 to tps60) of clock selectio n register 6 (cksr6) is supplied to each module when bit 7 (power6) of asynchronous serial interface operation mode register 6 (asim6) is 1. this clock is called the base clock and its frequency is called f xclk6 . the base clock is fixed to low level when power6 = 0. ? transmission counter this counter stops operation, clear ed to 0, when bit 7 (power6) or bit 6 (txe6) of asynchronous serial interface operation mode register 6 (asim6) is 0. it starts counting when power6 = 1 and txe6 = 1. the counter is cleared to 0 when the first data transmi tted is written to transmit buffer register 6 (txb6). if data are continuously transmitted, the counter is cleared to 0 agai n when one frame of data has been completely transmitted. if there is no data to be transmitted next, the count er is not cleared to 0 and continues counting until power6 or txe6 is cleared to 0. ? reception counter this counter stops operation, clear ed to 0, when bit 7 (power6) or bit 5 (rxe6) of asynchronous serial interface operation mode register 6 (asim6) is 0. it starts counting when the start bit has been detected. the counter stops operation after one frame has been received, until the next start bit is detected. chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 214 figure 11-24. configuration of baud rate generator selector power6 8-bit counter match detector baud rate baud rate generator brgc6: mdl67 to mdl60 1/2 power6, txe6 (or rxe6) cksr6: tps63 to tps60 f xp f xp /2 f xp /2 2 f xp /2 3 f xp /2 4 f xp /2 5 f xp /2 6 f xp /2 7 f xp /2 8 f xp /2 9 f xp /2 10 f xp /2 11 f xclk6 (base clock) remark power6: bit 7 of asynchronous serial interface operation mode register 6 (asim6) txe6: bit 6 of asim6 rxe6: bit 5 of asim6 cksr6: clock selection register 6 brgc6: baud rate generator control register 6 chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 215 (2) generation of serial clock a serial clock can be generated by using clock selection register 6 (cksr6) and baud rate generator control register 6 (brgc6). select the clock to be input to the 8-bit counter by using bits 3 to 0 (tps63 to tps60) of cksr6. bits 7 to 0 (mdl67 to mdl60) of brgc6 can be used to select the division value of the 8-bit counter. (a) baud rate the baud rate can be calculated by the following expression. ? baud rate = [bps] f xclk6 : frequency of base clock selected by tps63 to tps60 bits of cksr6 register k: value set by mdl67 to mdl60 bits of br gc6 register (k = 8, 9, 10, ..., 255) (b) error of baud rate the baud rate error can be calculated by the following expression. ? error (%) = ? 1 100 [%] cautions 1. keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. make sure that the baud rate error dur ing reception satisfies the range shown in (4) permissible baud rate ra nge during reception. example: frequency of base clock = 10 mhz = 10,000,000 hz set value of mdl67 to mdl60 bits of brgc6 register = 00100001b (k = 33) target baud rate = 153600 bps baud rate = 10 m/(2 33) = 10000000/(2 33) = 151,515 [bps] error = (151515/153600 ? 1) 100 = ? 1.357 [%] actual baud rate (baud rate with error) desired baud rate (correct baud rate) f xclk6 2 k chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 216 (3) example of setting baud rate table 11-4. set data of baud rate generator f xp = 10.0 mhz f xp = 8.38 mhz f xp = 4.19 mhz baud rate [bps] tps63 to tps60 k calculated value err[%] tps63 to tps60 k calculated value err[%] tps63 to tps60 k calculated value err[%] 600 6h 130 601 0.16 6h 109 601 0.11 5h 109 601 0.11 1200 5h 130 1202 0.16 5h 109 1201 0.11 4h 109 1201 0.11 2400 4h 130 2404 0.16 4h 109 2403 0.11 3h 109 2403 0.11 4800 3h 130 4808 0.16 3h 109 4805 0.11 2h 109 4805 0.11 9600 2h 130 9615 0.16 2h 109 9610 0.11 1h 109 9610 0.11 10400 1h 240 10417 0.16 1h 201 10423 0.22 1h 101 10475 ? 0.28 19200 1h 130 19231 0.16 1h 109 19220 0.11 0h 109 19220 0.11 31250 0h 160 31250 0.00 0h 134 31268 0.06 0h 67 31268 0.06 38400 0h 130 38462 0.16 0h 109 38440 0.11 0h 55 38090 ? 0.80 76800 0h 65 76923 0.16 0h 55 76182 ? 0.80 0h 27 77693 1.03 115200 0h 43 116279 0.94 0h 36 116389 1.03 0h 18 116389 1.03 153600 0h 33 151515 ? 1.36 0h 27 155185 1.03 0h 14 149643 ? 2.58 230400 0h 22 227272 ? 1.36 0h 18 232778 1.03 0h 9 232778 1.03 remark tps63 to tps60: bits 3 to 0 of clock select ion register 6 (cksr6) (setting of base clock (f xclk6 )) k: value set by mdl67 to mdl60 bits of baud rate generator control register 6 (brgc6) (k = 8, 9, 10, ..., 255) f xp : oscillation frequency of clock to peripheral hardware err: baud rate error chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 217 (4) permissible baud rate range during reception the permissible error from the baud rate at the trans mission destination during reception is shown below. caution make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. figure 11-25. permissible baud rate range during reception fl 1 data frame (11 fl) flmin flmax data frame length of uart6 start bit bit 0 bit 1 bit 7 parity bit minimum permissible data frame length maximum permissible data frame length stop bit start bit bit 0 bit 1 bit 7 parity bit latch timing stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 11-25, the latch timing of the re ceive data is determined by t he counter set by baud rate generator control register 6 (brgc6) a fter the start bit has been detected. if the last data (stop bit) meets this latch timing, the data can be correctly received. assuming that 11-bit data is received, the theoretical values can be calculated as follows. fl = (brate) ? 1 brate: baud rate of uart6 k: set value of brgc6 fl: 1-bit data length margin of latch timing: 2 clocks chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 218 minimum permissible data frame length: flmin = 11 fl ? fl = fl therefore, the maximum receivable baud rate at the transmission source is as follows. brmax = (flmin/11) ? 1 = brate similarly, the maximum permissible data fr ame length can be calculated as follows. 10 k + 2 21k ? 2 11 2 k 2 k flmax = fl 11 therefore, the minimum receivable baud rate at the transmission source is as follows. brmin = (flmax/11) ? 1 = brate the permissible baud rate error between uart6 and the tr ansmission source can be calculated from the above minimum and maximum baud rate expressions, as follows. table 11-5. maximum/minimum permissible baud rate error division ratio (k) maximum perm issible baud rate error minimu m permissible baud rate error 8 +3.53% ? 3.61% 20 +4.26% ? 4.31% 50 +4.56% ? 4.58% 100 +4.66% ? 4.67% 255 +4.72% ? 4.73% remarks 1. the permissible error of reception depends on t he number of bits in one frame, input clock frequency, and division ratio (k). the higher t he input clock frequency and the higher the division ratio (k), the higher the permissible error. 2. k: set value of brgc6 22k 21k + 2 flmax = 11 fl ? fl = fl 21k ? 2 20k 20k 21k ? 2 k ? 2 2k 21k + 2 2k chapter 11 serial interface uart6 user?s manual u17446ej5v0ud 219 (5) data frame length during continuous transmission when data is continuously transmitted, th e data frame length from a stop bit to the next start bit is extended by two clocks of the base clock (f xclk6 ) from the normal value. however, the result of communication is not affected because the timing is initialized on the rece ption side when the start bit is detected. figure 11-26. data frame length during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame fl fl fl fl fl fl flstp start bit of second byte start bit bit 0 where the 1-bit data length is fl, the stop bit length is flstp, and base clock frequency is f xclk6 , the following expression is satisfied. flstp = fl + 2/f xclk6 therefore, the data frame length during continuous transmission is: data frame length = 11 fl + 2/f xclk6 user?s manual u17446ej5v0ud 220 chapter 12 multiplier 12.1 multiplier function the multiplier has the following function. ? calculation of 8 bits 8 bits = 16 bits 12.2 multiplier configuration (1) 16-bit multiplication result storage register 0 (mul0) this register stores the 16-bi t result of multiplication. this register holds the result of multip lication after 16 cpu clocks have elapsed. mul0 can be read by a 16-bit memory manipulation instruction. reset signal generation makes mul0 undefined. caution although this register is manipulated with a 16-bit memory manipulation instruction, it can be also manipulated with an 8-bit memory manipulation instruction. when using an 8-bit memory manipulation instruct ion, however, access the regi ster by means of direct addressing. (2) multiplication data regist ers a and b (mra0 and mrb0) these are 8-bit multiplicati on data storage registers. t he multiplier multiplies the values of mra0 and mrb0. mra0 and mrb0 can be written by an 8-bit memory manipulation instruction. reset signal generation makes these registers undefined. figure 12-1 shows the block diagram of the multiplier. chapter 12 multiplier user?s manual u17446ej5v0ud 221 figure 12-1. block diagram of multiplier internal bus selector counter value 3 cpu clock start clear counter output 16-bit adder 16-bit multiplication result storage register 0 (master) (mul0) 16-bit multiplication result storage register 0 (slave) multiplication data register a (mra0) multiplication data register b (mrb0) internal bus 3-bit counter mulst0 reset multiplier control register 0 (mulc0) chapter 12 multiplier user?s manual u17446ej5v0ud 222 12.3 multiplier control register the multiplier is controlled by the following register. ? multiplier control register 0 (mulc0) (1) multiplier control register 0 (mulc0) this register indicates the operating st atus of the multiplier after operation, as well as controls the multiplier. mulc0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 12-2. format of multiplie r control register 0 (mulc0) address: ffd2h after reset: 00h rw symbol 7 6 5 4 3 2 1 <0> mulc0 0 0 0 0 0 0 0 mulst0 mulst0 multiplier operation start control bit operating status of multiplier 0 stops operation after resetting counter to 0. operation stops 1 enables operation operation in progress caution be sure to clear bits 1 to 7 to 0. chapter 12 multiplier user?s manual u17446ej5v0ud 223 12.4 multiplier operation the multiplier of the 78k 0s/kb1+ can execute the calculation of 8 bits 8 bits = 16 bits. figure 12-3 shows the operation timing of the multiplier where mra0 is set to aah and mrb0 is set to d3h. <1> counting is started by setting the mulst0, and t hen multiplication of mra0 and mrb0 begins. the multiplication result is held after 16 clocks, using the cpu clock. <2> the data generated by the selector is added to the data of mul0 at each cpu clock, and the counter value is incremented by one. <3> when the 3-bit counter value is 111b, mulst0 is cl eared and the operation is stopped. at this time, mul0 holds the operation result. remark when mulst0 is low, the 3-bit counter is cleared. figure 12-3. multiplier operation timing (example of aah d3h) aa d3 <1> <2> <3> 000b 001b 010b 011b 100b 101b 110b 111b 000b operation in progress note 8c1e cpu clock mra0 mrb0 mulst0 3-bit counter mul0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 note mid-calculation results are read by referencing mul0 while calculating. the source code of this example is shown in the following page. chapter 12 multiplier user?s manual u17446ej5v0ud 224 ;============================================================== ; the example of multiplier use ;============================================================== m_data_a equ 0fe80h ; address a for multipliers m_data_b equ 0fe90h ; address b for multipliers ; a setup for operation mov m_data_a, #0aah mov m_data_b, #0d3h ; multiplication of m_data_a and m_data_b mov a, m_data_a mov mra0, a mov a, m_data_b mov mrb0, a set1 mulst0 ; multiplication start m_loop: bt mulst0, $m_loop ; waiting for multiplication completion movw ax, mul0 ; multiplication completion user?s manual u17446ej5v0ud 225 chapter 13 interrupt functions 13.1 interrupt function types there are two types of interrupt s: maskable interrupts and resets. ? maskable interrupts these interrupts undergo mask control. when an interr upt request occurs, the standby release signal occurs, and if an interrupt can be acknowledged then the program corresponding to t he address written in the vector table address is executed (vector in terrupt servicing). when several in terrupt requests ar e generated at the same time, processing takes place in the priority order of the vector interrupt serv icing. for details on the priority order, see table 13-1. there are nine internal sources and four external sources of maskable interrupts. ? reset the cpu and sfr are returned to thei r initial states by the reset si gnal. the causes for reset signal occurrences are shown in table 13-1. when a reset signal occurs, program execution starts from the programs at the addr esses written in addresses 0000h and 0001h. chapter 13 interrupt functions user?s manual u17446ej5v0ud 226 13.2 interrupt sources and configuration there are a total of 13 maskable interrupt sources, and up to four reset sources (see table 13-1 ). table 13-1. interrupt sources interrupt source interrupt type priority note 1 name trigger internal/ external vector table address basic configuration type note 2 1 intlvi low-voltage detection note 3 internal 0006h (a) 2 intp0 0008h 3 intp1 pin input edge detection external 000ah (b) 4 inttmh1 match between tmh1 and cmp01 000ch 5 inttm000 match between tm00 and cr000 (when compare register is specified), ti010 pin valid edge detection (when capture register is specified) 000eh 6 inttm010 match between tm00 and cr010 (when compare register is specified), ti000 pin valid edge detection (when capture register is specified) 0010h 7 intad end of a/d conversion internal 0012h (a) 8 intp2 0016h 9 intp3 pin input edge detection external 0018h (b) 10 inttm80 match between tm80 and cr80 001ah 11 intsre6 uart6 reception error occurrence 001ch 12 intsr6 end of uart6 reception 001eh maskable 13 intst6 end of uart6 transmission internal 0020h (a) reset reset input poc power-on-clear lvi low-voltage detection note 4 reset ? wdt wdt overflow ? 0000h ? notes 1. priority is the vector interrupt servicing priori ty order when several maskable interrupt requests are generated at the same time. 1 is the highest and 13 is the lowest. 2. basic configuration types (a) and (b) correspond to (a) and (b) in figure 13-1. 3. when bit 1 (lvimd) of low-voltage detec tion register (lvim) = 0 is selected. 4. when bit 1 (lvimd) of low-voltage detec tion register (lvim) = 1 is selected. caution no interrupt sources corres pond to the vector table address 0014h. chapter 13 interrupt functions user?s manual u17446ej5v0ud 227 figure 13-1. basic configuration of interrupt function (a) internal maskable interrupt mk if ie internal bus interrupt request vector table address generator standby release signal (b) external maskable interrupt internal bus external interrupt mode registers 0,1 (intm0, intm1) mk if ie vector table address generator standby release signal edge detector interrupt request if: interrupt request flag ie: interrupt enable flag mk: interrupt mask flag chapter 13 interrupt functions user?s manual u17446ej5v0ud 228 13.3 interrupt function control registers the interrupt functions are controlled by the following four types of registers. ? interrupt request flag registers 0, 1 (if0, if1) ? interrupt mask flag registers 0, 1 (mk0, mk1) ? external interrupt mode regi sters 0, 1 (intm0, intm1) ? program status word (psw) table 13-2 lists interrupt requests, the correspondi ng interrupt request flags, and interrupt mask flags. table 13-2. interrupt request signals and corresponding flags interrupt request signal interrupt request flag interrupt mask flag intlvi intp0 intp1 inttmh1 inttm000 inttm010 intad intp2 intp3 inttm80 intsre6 intsr6 intst6 lviif pif0 pif1 tmifh1 tmif000 tmif010 adif pif2 pif3 tmif80 sreif6 srif6 stif6 lvimk pmk0 pmk1 tmmkh1 tmmk000 tmmk010 admk pmk2 pmk3 tmmk80 sremk6 srmk6 stmk6 chapter 13 interrupt functions user?s manual u17446ej5v0ud 229 (1) interrupt request flag registers 0, 1 (if0, if1) an interrupt request flag is set to 1 when the co rresponding interrupt request is issued, or when the instruction is executed. it is cleared to 0 by ex ecuting an instruction when the interrupt request is acknowledged or when a reset signal is generated. if0 and if1 are set with a 1-bit or 8-bi t memory manipulation instruction. reset signal generation clears if0 and if1 to 00h. figure 13-2. format of interrupt requ est flag registers 0, 1 (if0, if1) address: ffe0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> 0 if0 adif tmif010 tmif000 tmifh1 pif1 pif0 lviif 0 address: ffe1h after reset: 00h r/w symbol 7 <6> <5> <4> <3> <2> <1> 0 if1 0 stif6 srif6 sreif6 tmif80 pif3 pif2 0 if interrupt request flag 0 no interrupt request signal has been issued. 1 an interrupt request signal has been issued; an interrupt request status. caution because p30, p31, p41, and p43 have an alternate functi on as external interrupt inputs, when the output level is changed by specifyi ng the output mode of the port function, an interrupt request flag is set. therefore, the interrupt mask flag should be set to 1 before using the output mode. chapter 13 interrupt functions user?s manual u17446ej5v0ud 230 (2) interrupt mask flag registers 0, 1 (mk0, mk1) the interrupt mask flag is used to enable and di sable the corresponding maskable interrupts. mk0 and mk1 are set with a 1-bit or 8-bi t memory manipulation instruction. generation of reset signal sets mk0 and mk1 to ffh. figure 13-3. format of interrupt m ask flag registers 0, 1 (mk0, mk1) address: ffe4h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> 0 mk0 admk tmmk010 tmmk000 tmmkh1 pmk1 pmk0 lvimk 1 address: ffe5h after reset: ffh r/w symbol 7 <6> <5> <4> <3> <2> <1> 0 mk1 1 stmk6 srmk6 sremk6 tmmk80 pmk3 pmk2 1 mk interrupt servicing control 0 enables interrupt servicing. 1 disables interrupt servicing. caution because p30, p31, p41, and p43 have an alternate functi on as external interrupt inputs, when the output level is changed by specifyi ng the output mode of the port function, an interrupt request flag is set. therefore, the interrupt mask flag should be set to 1 before using the output mode. chapter 13 interrupt functions user?s manual u17446ej5v0ud 231 (3) external interrupt m ode register 0 (intm0) this register is used to set the valid edge of intp0 to intp2. intm0 is set with an 8-bit memo ry manipulation instruction. reset signal generation clears intm0 to 00h. figure 13-4. format of external in terrupt mode register 0 (intm0) address: ffech after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 intm0 es21 es20 es11 es10 es01 es00 0 0 es21 es20 intp2 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges es11 es10 intp1 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges es01 es00 intp0 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges cautions 1. be sure to clear bits 0 and 1 to 0. 2. before setting the intm0 register, be su re to set the corresponding interrupt mask flag ( mk = 1) to disable interrupts. after setti ng the intm0 register, clear the interrupt request flag ( if = 0), then clear the interrupt mask flag ( mk = 0), which will enable interrupts. chapter 13 interrupt functions user?s manual u17446ej5v0ud 232 (4) external interrupt m ode register 1 (intm1) intm1 is used to specify the valid edge for intp3. intm1 is set with an 8-bit memo ry manipulation instruction. reset signal generation clears intm1 to 00h. figure 13-5. format of external in terrupt mode register 1 (intm1) address: ffedh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 intm1 0 0 0 0 0 0 es31 es30 es31 es30 intp3 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges cautions 1. be sure to clear bits 2 to 7 to 0. 2. before setting intm1, set pmk3 to 1 to disable interrupts. to enable interrupts, clear pif3 to 0, then clear pmk3 to 0. (5) program status word (psw) the program status word is used to hol d the instruction executi on result and the current st atus of the interrupt requests. the ie flag, used to enable and dis able maskable interrupts, is mapped to psw. psw can be read- and write-accessed in 8-bit units, as well as using bit manipulation instructions and dedicated instructions (ei and di). when a vectored interrupt is ack nowledged, the psw is automatically saved to a stack, and the ie flag is reset to 0. generation of reset signal sets psw to 02h. figure 13-6. program status word (psw) configuration ie z 0 ac 0 0 1 cy psw symbol after reset 02h 76543210 ie 0 1 disabled enabled whether to enable/disable interrupt acknowledgment used in the execution of ordinary instructions chapter 13 interrupt functions user?s manual u17446ej5v0ud 233 13.4 interrupt servicing operation 13.4.1 maskable interrupt re quest acknowledgment operation a maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. if the interr upt enabled status is in effect (when the ie flag is set to 1), then the request is acknowledged as a vector interrupt. the time required to start the vect ored interrupt servicing after a mask able interrupt request has been generated is shown in table 13-3. see figures 13-8 and 13-9 for the inte rrupt request acknowledgment timing. table 13-3. time from generation of maskable interrupt request to servicing minimum time maximum time note 9 clocks 19 clocks note the wait time is maximum when an interrupt request is generated imm ediately before bt and bf instructions. remark 1 clock: (f cpu : cpu clock) when two or more maskable interrupt requests are generat ed at the same time, they are acknowledged starting from the interrupt request assigned the highest priority. a pending interrupt is acknowledged when a status in which it can be acknowledged is set. figure 13-7 shows the algorithm of interrupt request acknowledgment. when a maskable interrupt request is a cknowledged, the contents of the psw and pc are saved to the stack in that order, the ie flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the pc, and execution branches. to return from interrupt servic ing, use the reti instruction. 1 f cpu chapter 13 interrupt functions user?s manual u17446ej5v0ud 234 figure 13-7. interrupt request acknowledgment processing algorithm start if = 1? mk = 0? ie = 1? vectored interrupt servicing yes (interrupt request generated) yes yes no no no interrupt request pending interrupt request pending if: interrupt request flag mk: interrupt mask flag ie: flag to control maskable interrupt reques t acknowledgment (1 = enable, 0 = disable) figure 13-8. interrupt request ackno wledgment timing (example of mov a, r) clock cpu interrupt mov a, r saving psw and pc, jump to interrupt servicing 8 clocks interrupt servicing program if an interrupt request flag ( if) is set before an instruction clock n (n = 4 to 10) under execution becomes n ? 1, the interrupt is acknowledged after the instruction under execution is complete . figure 13-8 shows an example of the interrupt request acknowledgment timing for an 8-bit data transfe r instruction mov a, r. since this instruction is executed for 4 clocks, if an interrupt occurs for 3 clocks afte r the instruction fetch starts , the interrupt acknowledgment processing is performed after the mo v a, r instruction is executed. chapter 13 interrupt functions user?s manual u17446ej5v0ud 235 figure 13-9. interrupt request ack nowledgment timing (when interrupt request flag is set at last clock during instruction execution) saving psw and pc, jump to interrupt servicing 8 clocks interrupt servicing program clock cpu interrupt nop mov a, r if an interrupt request flag ( if) is set at the last clock of the instru ction, the interrupt a cknowledgment processing starts after the next instruction is executed. figure 13-9 shows an example of the in terrupt request acknowledgment timing fo r an interrupt request flag that is set at the second clock of nop (2-clock inst ruction). in this case, the mov a, r instruction after the nop instruction is executed, and then the interrupt ack nowledgment processing is performed. caution interrupt requests will be held pending while the interrupt request fl ag registers 0, 1 (if0, if1) or interrupt mask flag registers 0, 1 (mk0, mk1) are being accessed. 13.4.2 multiple interrupt servicing in order to perform multiple interrupt servicing in wh ich another interrupt is ack nowledged while an interrupt is being serviced, the interrupt mask functi on must be used to mask interrupts for which a low priority is to be set. chapter 13 interrupt functions user?s manual u17446ej5v0ud 236 figure 13-10. example of multiple interrupts (1/2) example 1. multiple interrupts are acknowledged intyy ei main processing ei intyy servicing intxx servicing reti ie = 0 intxx reti ie = 0 during interrupt intxx servicing, inte rrupt request intyy is acknowledged, and multiple interrupts are generated. before each interrupt request acknowledgment, the ei instru ction is issued, the interr upt mask is released, and the interrupt request acknowledgment enable state is set. caution multiple interrupts can be ackno wledged even for low-priority interrupts. example 2. multiple interrupts are not generated because interrupts are not enabled intyy ei main processing reti intyy servicing intxx servicing ie = 0 intxx reti intyy is held pending ie = 0 because interrupts are not enabled in inte rrupt intxx servicing (the ei instruct ion is not issued), interrupt request intyy is not acknowledged, and mult iple interrupts are not generated. the intyy request is held pending and acknowledged after the intxx servicing is performed. ie = 0: interrupt request acknowledgment disabled chapter 13 interrupt functions user?s manual u17446ej5v0ud 237 figure 13-10. example of multiple interrupts (2/2) example 3. a priority is contro lled by the multiple interrupts the vector interrupt enable state is set for intp0, intp1, and inttmh1. (interrupt priority intp0 > intp1 > inttmh1 (refer to table13-1 )) intp0 ei pmk0 = 1 ie = 0 ei intp1 reti ie = 0 pmk0 = 0 ie = 0 reti reti inttmh1 main processing inttnh1 servicing intp1 servicing intp0 servicing in the interrupt inttmh1 servicing, servicing is performed su ch that the intp1 interrupt is given priority, since the intp0 interrupt was first masked. afterwards, once the interrupt mask for intp0 is rel eased, intp0 processing through multiple interrupts is performed. ie = 0: interrupt request acknowledgment disabled 13.4.3 interrupt request pending some instructions may keep pending t he acknowledgment of an instruction request until the completion of the execution of the next instru ction even if the interrupt request (maskable interrupt and external interrupt) is generated during the execution. the following shows such in structions (interrupt request pending instruction). ? manipulation instruction for interrupt request flag registers 0, 1 (if0, if1) ? manipulation instruction for interrupt mask flag registers 0, 1 (mk0, mk1) user?s manual u17446ej5v0ud 238 chapter 14 standby function 14.1 standby function and configuration 14.1.1 standby function table 14-1. relationship between operat ion clocks in each operation status low-speed internal oscillator note 2 status operation mode note 1 lsrstop = 0 lsrstop = 1 system clock clock supplied to peripheral hardware reset stopped stop stopped stopped halt oscillating oscillating note 3 stopped oscillating oscillating notes 1. when ?cannot be stopped? is selected for low-s peed internal oscillator by the option byte. 2. when it is selected that the low- speed internal oscillator ?can be st opped by software?, oscillation of the low-speed internal oscillator can be stopped by lsrstop. 3. if the operating clock of the watc hdog timer is the low- speed internal oscillati on clock, the watchdog timer is stopped. caution the lsrstop setting is valid only when ?can be stopped by so ftware? is set for the low-speed internal oscillator by the option byte. remark lsrstop: bit 0 of the low-speed internal oscillation mode register (lsrcm) the standby function is de signed to reduce the operat ing current of the system. the following two modes are available. (1) halt mode halt instruction execution sets t he halt mode. in the halt mode, the cpu operation clock is stopped. oscillation of the system clock oscillator continues. if the low-speed internal oscillator is operating before the halt mode is set, oscillation of the clock of the lo w-speed internal oscillator continues (refer to table 14-1 . oscillation of the low-speed internal oscillation clock (whether it cannot be stopped or can be stopped by software) is set by the option byte). in this mode, t he operating current is not decr eased as much as in the stop mode, but the halt mode is effective for rest arting operation immediately upon interrupt request generation and frequently carrying out intermittent operations. chapter 14 standby function user?s manual u17446ej5v0ud 239 (2) stop mode stop instruction execution sets t he stop mode. in the stop mode , the system clock oscillator stops, stopping the whole system, thereby consider ably reducing the cpu operating current. because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out. however, select the halt mode if processing must be immediately star ted by an interrupt request when the operation stop time note is generated after the stop mode is rel eased (because an additional wait time for stabilizing oscillation elapses when cr ystal/ceramic oscillation is used). note the operation stop time is 17 s (min.), 34 s (typ.), and 67 s (max.). in either of these two modes, all the contents of registers, flags and data me mory just before the standby mode is set are held. the i/o port output latches an d output buffer statuses are also held. cautions 1. when shifting to the stop mode, be su re to stop the peripheral hardware operation before executing stop instruction (excep t the peripheral hardware that operates on the low-speed internal oscillation clock). 2. the following sequence is recommended for ope rating current reduction of the a/d converter when the standby function is used: first cl ear bit 7 (adcs) and bit 0 (adce) of the a/d converter mode register (adm) to 0 to stop the a/d conversion opera tion, and then execute the halt or stop instruction. 3. if the low-speed internal oscillator is operati ng before the stop mode is set, oscillation of the low-speed internal oscillation clock cannot be stoppe d in the stop mode (refer to table 14-1). chapter 14 standby function user?s manual u17446ej5v0ud 240 14.1.2 registers used during standby the oscillation stabilization time after the standby mode is rel eased is controlled by the o scillation stabilization time select register (osts). remark for the registers that start, st op, or select the clock, see chapter 5 clock generators . (1) oscillation stabilization time select register (osts) this register is used to select oscillation stabilization time of the clock supplied fr om the oscillator when the stop mode is released. the wait time set by osts is valid only when the crystal/ceramic oscillation clock is selected as the system clock and after the stop mode is released. if the high-speed internal oscillation or external clock input is selected as the system clock source, no wait time elapses. the system clock oscillator and the osc illation stabilization time that elapses after power application or release of reset are selected by the opti on byte. for details, refer to chapter 18 option byte . osts is set by using the 8-bit memory manipulation instruction. figure 14-1. format of oscillation stabiliz ation time select register (osts) address: fff4h after reset: undefined r/w symbol 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 0 osts1 osts0 osts1 osts0 selection of oscillation stabilization time 0 0 2 10 /f x (102.4 s) 0 1 2 12 /f x (409.6 s) 1 0 2 15 /f x (3.27 ms) 1 1 2 17 /f x (13.1 ms) cautions 1. to set and then release the stop mode , set the oscillation stabil ization time as follows. expected oscillation stab ilization time of resonator oscillation stabilization time set by osts 2. the wait time after the stop mode is released does not incl ude the time from the release of the stop mode to the start of clock oscillation (?a? in the figure below), regardless of whether stop mode was releas ed by reset signal ge neration or interrupt generation. stop mode is released voltage waveform of x1 pin a 3. the oscillation stabilizati on time that elapses on power app lication or after release of reset is selected by the option byte. for details, refer to chapter 18 option byte. remarks 1. ( ): f x = 10 mhz 2. determine the oscillation stabilization time of the resonator by checking the characteristics of the resonator to be used. chapter 14 standby function user?s manual u17446ej5v0ud 241 14.2 standby function operation 14.2.1 halt mode (1) halt mode the halt mode is set by execut ing the halt instruction. the operating statuses in t he halt mode are shown below. caution because an interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and th e interrupt mask flag clear, the standby mode is immediately cleared if set. table 14-2. operating statuses in halt mode low-speed internal oscillator can be stopped note setting of halt mode item low-speed internal oscillator cannot be stopped note when low-speed internal oscillation continues when low-speed internal oscillation stops system clock clock supply to cpu is stopped. cpu operation stops. port (latch) holds status before halt mode was set. 16-bit timer/event counter 00 operable 8-bit timer 80 operable sets count clock to f xp to f xp /2 12 operable 8-bit timer h1 sets count clock to f rl /2 7 operable operable operation stops. system clock selected as operating clock setting prohibited operation stops. watchdog timer ?low-speed internal oscillation clock? selected as operating clock operable (operation continues.) operation stops. a/d converter operable serial interface uart6 operable power-on-clear circui t always operates. low-voltage detector operable external interrupt operable note ?cannot be stopped? or ?stopped by software? is selected for low-speed internal oscillator by the option byte (for the option byte, see chapter 18 option byte ). chapter 14 standby function user?s manual u17446ej5v0ud 242 (2) halt mode release the halt mode can be released by the following two sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generat ed, the halt mode is released. if interrupt acknowledgment is enabled, vectored interrupt servicin g is carried out. if interrupt acknowledgment is disabled, the next address instruction is executed. figure 14-2. halt mode release by interrupt request generation halt instruction wait wait operating mode halt mode operating mode oscillation system clock oscillation status of cpu standby release signal interrupt request remarks 1. the broken lines indicate the case when t he interrupt request which has released the standby mode is acknowledged. 2. the wait time is as follows: ? when vectored interrupt servicing is carried out: 11 to 13 clocks ? when vectored interrupt servicing is not carried out: 3 to 5 clocks chapter 14 standby function user?s manual u17446ej5v0ud 243 (b) release by reset signal generation when the reset signal is generated, halt mode is rel eased, and then, as in the case with a normal reset operation, the program is executed after br anching to the reset vector address. figure 14-3. halt mode releas e by reset signal generation (1) when cpu clock is high-speed intern al oscillation clock or external input clock halt instruction reset signal system clock oscillation operation mode halt mode reset period operation mode oscillates oscillation stops oscillates cpu status operation stops note note operation is stopped (277 s (min.), 544 s (typ.), 1.075 ms (max.)) because the option byte is referenced. (2) when cpu clock is crys tal/ceramic oscillation clock halt instruction reset signal system clock oscillation operation mode halt mode reset period operation stops note oscillation stabilization waits oscillates oscillation stops oscillates cpu status oscillation stabilization time (2 10 /f x to 2 17 /f x ) operation mode note operation is stopped (276 s (min.), 544 s (typ.), 1.074 ms (max.)) because the option byte is referenced. remark f x : system clock oscillation frequency table 14-3. operation in response to interrupt request in halt mode release source mk ie operation 0 0 next address instruction execution 0 1 interrupt servicing execution maskable interrupt request 1 halt mode held reset signal generation ? reset processing : don?t care chapter 14 standby function user?s manual u17446ej5v0ud 244 14.2.2 stop mode (1) stop mode setting and operating statuses the stop mode is set by exec uting the stop instruction. caution because an interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. thus, in the stop mode, the no rmal operation mode is restored after the stop instruction is execu ted and then the opera tion is stopped for 34 s (typ.) (after an additional wait time for stab ilizing the oscillation set by the oscillation stabilization time select register (osts) has elapsed when cr ystal/ceramic oscillation is used). the operating statuses in t he stop mode are shown below. table 14-4. operating statuses in stop mode low-speed internal oscillator can be stopped note setting of halt mode item low-speed internal oscillator cannot be stopped note when low-speed internal oscillation continues when low-speed internal oscillation stops system clock oscillation stops. cpu operation stops. port (latch) holds status before stop mode is set. 16-bit timer/event counter 00 operation stops. 8-bit timer 80 operation stops. sets count clock to f xp to f xp /2 12 operation stops. 8-bit timer h1 sets count clock to f rl /2 7 operable operable operation stops. ?clock to peripheral hardware? selected as operating clock setting prohibited operation stops. watchdog timer ?low-speed internal oscillation clock? selected as operating clock operable (operation continues.) operation stops. a/d converter operation stops. serial interface uart6 operation stops. power-on-clear circui t always operates. low-voltage detector operable external interrupt operable note ?cannot be stopped? or ?stopped by software? is selected for low-speed internal oscillator by the option byte (for the option byte, see chapter 18 option byte ). chapter 14 standby function user?s manual u17446ej5v0ud 245 (2) stop mode release figure 14-4. operation timing wh en stop mode is released <1> if high-speed internal oscillati on clock or external input clock is sel ected as system clo ck to be supplied system clock oscillation cpu clock stop mode is released. stop mode high-speed internal oscillation clock or external clock input operation stops note . <2> if crystal/ceramic oscillation clock is selected as system cl ock to be supplied system clock oscillation cpu clock stop mode is released. stop mode halt status (oscillation stabilization time set by osts) crystal/ceramic oscillation clock operation stops note . note the operation stop time is 17 s (min.), 34 s (typ.), and 67 s (max.). the stop mode can be released by the following two sources. chapter 14 standby function user?s manual u17446ej5v0ud 246 (a) release by unmasked interrupt request when an unmasked interrupt request (8-bit timer h1 note , low-voltage detector, exte rnal interrupt request) is generated, the stop mode is released. after the oscillation stabilizati on time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servic ing is carried out. if interrupt acknowledgment is disabled, the next address instruction is executed. note only when sets count clock to f rl /2 7 figure 14-5. stop mode release by interrupt request generation (1) if cpu clock is high-speed internal oscillation clock or external input clock operation mode operation mode oscillation stop instruction stop mode standby release signal system clock oscillation cpu status oscillation oscillation stops. operation stops note . interrupt request (2) if cpu clock is crys tal/ceramic oscillation clock waiting for stabilization of oscillation oscillation stabilization time (set by osts) (halt mode status) operation mode operation mode oscillation stop instruction stop mode standby release signal system clock cpu status oscillation oscillation stops. operation stops note . interrupt request note the operation stop time is 17 s (min.), 34 s (typ.), and 67 s (max.). remark the broken lines indicate the case when the inte rrupt request that has re leased the standby mode is acknowledged. chapter 14 standby function user?s manual u17446ej5v0ud 247 (b) release by reset signal generation when the reset signal is generated, stop mode is released and a reset operation is performed after the oscillation stabilization time has elapsed. figure 14-6. stop mode rel ease by reset signal generation (1) if cpu clock is high-speed internal oscillation clock or external input clock stop instruction reset signal system clock oscillation operation mode stop mode reset period operation mode oscillation oscillation stops. oscillation cpu status operation stops note . note operation is stopped (277 s (min.), 544 s (typ.), 1.075 ms (max.)) because the option byte is referenced. (2) if cpu clock is crys tal/ceramic oscillation clock stop instruction reset signal system clock oscillation operation mode stop mode reset period operation stops note . operation mode oscillation oscillation stops. oscillation cpu status oscillation stabilization time (2 10 /f x to 2 17 /f x ) oscillation stabilization waits note operation is stopped (276 s (min.), 544 s (typ.), 1.074 ms (max.)) because the option byte is referenced. remark f x : system clock oscillation frequency table 14-5. operation in response to interrupt request in stop mode release source mk ie operation 0 0 next address instruction execution 0 1 interrupt servicing execution maskable interrupt request 1 stop mode held reset signal generation ? reset processing : don?t care user?s manual u17446ej5v0ud 248 chapter 15 reset function the following four operations are av ailable to generate a reset signal. (1) external reset input via reset pin (2) internal reset by watchdog timer overflows (3) internal reset by comparison of supply voltage and detection voltage of power-on-clear (poc) circuit (4) internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (lvi) external and internal resets have no functional differences . in both cases, program execution starts from the programs at the address written in addresses 0000 h and 0001h when the reset signal is generated. a reset is applied when a low level is input to the reset pin, the watchdog timer overflows, or by poc and lvi circuit voltage detection, and each item of hardware is set to the status show n in table 15-1. each pin is high impedance during reset signal generation or during the oscillatio n stabilization time just after reset release, except for p130, which is low-level output. when a low level is input to the reset pin, a reset occu rs, and when a high level is input to the reset pin, the reset is released and the cpu starts program execution a fter referencing the option byte (after the option byte is referenced and the clock oscillation stabilization time elapses if crystal/ceramic oscillation is selected). a reset generated by the watchdog timer source is automatically released after t he reset, and the cpu starts program execution after referencing the option byte (after the option byte is referenced and the clock oscillation stabilization time elapses if crystal/ceramic oscillation is selected). (see figures 15-2 to 15-4 ). reset by poc and lvi circuit power supply detection is automatically released when v dd > v poc or v dd > v lvi after the reset, and the cpu starts program execution after referencing the option byte (after the option byte is referenced and the clock oscillation stabilization time elapses if crystal/cer amic oscillation is selected) (see chapter 16 power-on-clear circuit and chapter 17 low-voltage detector ). cautions 1. for an external reset, input a low level for 2 s or more to the reset pin. 2. during reset signal generation, the system clock and low-speed inte rnal oscillation clock stop oscillating. 3. when the reset pin is used as an input-only port pin (p34) , the 78k0s/kb1+ is reset if a low level is input to the reset pin after reset is re leased by the poc circui t, the lvi circuit and the watchdog timer and before th e option byte is referenced ag ain. the reset status is retained until a high level is input to the reset pin. chapter 15 reset function user?s manual u17446ej5v0ud 249 figure 15-1. block di agram of reset function reset lvirf wdtrf reset control flag register (resf) internal bus reset signal of wdt reset signal of poc reset signal of lvi internal reset signal reset signal to lvim/lvis register clear set clear set caution the lvi circuit is not reset by the internal reset signal of the lvi circuit. remarks 1. lvim: low-voltage detect register 2. lvis: low-voltage detection level select register chapter 15 reset function user?s manual u17446ej5v0ud 250 figure 15-2. timing of reset by reset input <1> with high-speed internal oscilla tion clock or external clock input hi-z reset port pin (except p130) port pin (p130) note 2 delay normal operation in progress cpu clock reset period (oscillation stops) normal operation (reset processing, cpu clock) internal reset signal high-speed internal oscillation clock or external clock input delay operation stops because option byte is referenced note 1 . 100 ns (typ.) 100 ns (typ.) notes 1. the operation stop time is 277 s (min.), 544 s (typ.), and 1.075 ms (max.). 2. set high level output using software. remark when reset is effected, p130 outputs a low level. if p130 is set to output a high level before reset is effected, the output signal of p130 can be du mmy-output as the reset signal to the cpu. <2> with crystal/ceramic oscillation clock hi-z reset port pin (p130) note 2 port pin (except p130) delay normal operation in progress reset period (oscillation stops) oscillation stabilization time (2 10 /f x to 2 17 /f x ) normal operation (reset processing, cpu clock) internal reset signal crystal/ceramic oscillation clock delay operation stops because option byte is referenced note 1 . 100 ns (typ.) 100 ns (typ.) notes 1. the operation stop time is 276 s (min.), 544 s (typ.), and 1.074 ms (max.). 2. set high level output using software. remarks 1. f x : system clock oscillation frequency 2. when reset is effected, p130 outputs a low level. if p130 is set to output a high level before reset is effected, the output signal of p130 can be du mmy-output as the reset signal to the cpu. chapter 15 reset function user?s manual u17446ej5v0ud 251 figure 15-3. timing of reset by overflow of watchdog timer <1> with high-speed internal oscilla tion clock or external clock input hi-z port pin (except p130) port pin (p130) note 2 normal operation in progress cpu clock reset period (oscillation stops) normal operation (reset processing, cpu clock) internal reset signal high-speed internal oscillation clock or external clock input operation stops because option byte is referenced note 1 . watchdog overflow notes 1. the operation stop time is 277 s (min.), 544 s (typ.), and 1.075 ms (max.). 2. set high level output using software. caution the watchdog timer is also reset in th e case of an internal reset of the watchdog timer. remark when reset is effected, p130 outputs a low level. if p130 is set to output a high level before reset is effected, the output signal of p130 can be du mmy-output as the reset signal to the cpu. <2> with crystal/ceramic oscillation clock hi-z port pin (p130) note 2 port pin (except p130) normal operation in progress reset period (oscillation stops) oscillation stabilization time (2 10 /f x to 2 17 /f x ) normal operation (reset processing, cpu clock) internal reset signal crystal/ceramic oscillation clock operation stops because option byte is referenced note 1 . cpu clock watchdog overflow notes 1. the operation stop time is 276 s (min.), 544 s (typ.), and 1.074 ms (max.). 2. set high level output using software. caution the watchdog timer is also reset in the case of an internal reset of the watchdog timer. remarks 1. f x : system clock oscillation frequency 2. when reset is effected, p130 outputs a low level. if p130 is set to output a high level before reset is effected, the output signal of p130 can be du mmy-output as the reset signal to the cpu. chapter 15 reset function user?s manual u17446ej5v0ud 252 figure 15-4. reset timing by reset input in stop mode <1> with high-speed internal oscilla tion clock or external clock input hi-z reset port pin (except p130) port pin (p130) note 2 delay normal operation in progress cpu clock reset period (oscillation stops) normal operation (reset processing, cpu clock) internal reset signal high-speed internal oscillation clock or external clock input delay operation stops because option byte is referenced note 1 . stop status (oscillation stops) stop instruction is executed. 100 ns (typ.) 100 ns (typ.) notes 1. the operation stop time is 277 s (min.), 544 s (typ.), and 1.075 ms (max.). 2. set high level output using software. remark when reset is effected, p130 outputs a low level. if p130 is set to output a high level before reset is effected, the output signal of p130 can be du mmy-output as the reset signal to the cpu. <2> with crystal/ceramic oscillation clock hi-z reset port pin (except p130) port pin (p130) note 2 delay normal operation in progress cpu clock normal operation (reset processing, cpu clock) internal reset signal delay operation stops because option byte is referenced note 1 . reset period (oscillation stops) stop status (oscillation stops) stop instruction is executed. oscillation stabilization time (2 10 /f x to 2 17 /f x ) 100 ns (typ.) 100 ns (typ.) crystal/ceramic oscillation clock notes 1. the operation stop time is 276 s (min.), 544 s (typ.), and 1.074 ms (max.). 2. set high level output using software. chapter 15 reset function user?s manual u17446ej5v0ud 253 remarks 1. for the reset timing of the power-on-clear circuit and low-voltage detector, refer to chapter 16 power-on-clear circuit and chapter 17 low-voltage detector . 2. f x : system clock oscillation frequency 3. when reset is effected, p130 outputs a low level. if p130 is set to output a high level before reset is effected, the output signal of p130 can be du mmy-output as the reset signal to the cpu. table 15-1. hardware statuses after reset acknowledgment (1/2) hardware status after reset program counter (pc) note 1 contents of reset vector table (0000h and 0001h) are set. stack pointer (sp) undefined program status word (psw) 02h data memory undefined note 2 ram general-purpose registers undefined note 2 ports (p0, p2 to p4, p12, p13) (output latches) 00h port mode registers (pm0, pm2 to pm4, pm12) ffh port mode control register (pmc2) 00h pull-up resistor option registers (pu0, pu2, pu3, pu4, pu12) 00h processor clock control register (pcc) 02h preprocessor clock control register (ppcc) 02h low-speed internal oscillation mode register (lsrcm) 00h oscillation stabilization time select register (osts) undefined timer counter 00 (tm00) 0000h capture/compare registers 000, 010 (cr000, cr010) 0000h mode control register 00 (tmc00) 00h prescaler mode register 00 (prm00) 00h capture/compare control register 00 (crc00) 00h 16-bit timer 00 timer output control register 00 (toc00) 00h timer counter 80 (tm80) 00h compare register (cr80) undefined 8-bit timer 80 mode control register 80 (tmc80) 00h compare registers (cmp01, cmp11) 00h 8-bit timer h1 mode register 1 (tmhmd1) 00h mode register (wdtm) 67h watchdog timer enable register (wdte) 9ah conversion result registers (adcr, adcrh) undefined mode register (adm) 00h a/d converter analog input channel specification register (ads) 00h notes 1. only the contents of pc are undefined while reset signal generation and while t he oscillation stabilization time elapses. the statuses of the other hardware units remain unchanged. 2. the status after reset is held in the standby mode. chapter 15 reset function user?s manual u17446ej5v0ud 254 table 15-1. hardware statuses after reset acknowledgment (2/2) hardware status after reset receive buffer register 6 (rxb6) ffh transmit buffer register 6 (txb6) ffh asynchronous serial interface oper ation mode register 6 (asim6) 01h asynchronous serial interface rece ption error status register 6 (asis6) 00h asynchronous serial interface tran smission error status register 6 (asif6) 00h clock select register 6 (cksr6) 00h baud rate generator control register 6 (brgc6) ffh asynchronous serial interface control register 6 (asicl6) 16h serial interface uart6 input select control register (isc) 00h 16-bit multiplication result storage register (mul0) undefined data registers (mra0, mrb0) undefined multiplier control register (mulc0) 00h reset function reset control flag register (resf) 00h note low-voltage detection register (lvim) 00h note low-voltage detector low-voltage detection level select register (lvis) 00h note request flag registers (if0, if1) 00h mask flag registers (mk0, mk1) ffh interrupt external interrupt mode registers (intm0, intm1) 00h flash protect command register (pfcmd) undefined flash status register (pfs) 00h flash programming mode control register (flpmc) undefined flash programming command register (flcmd) 00h flash address pointer l (flapl) flash address pointer h (flaph) undefined flash address pointer h compare register (flaphc) 00h flash address pointer l compare register (flaplc) 00h flash memory flash write buffer register (flw) 00h note these values change as follows depending on the reset source. reset source register reset input reset by poc reset by wdt reset by lvi wdtrf set (1) held resf lvirf cleared (0) cleared (0) held set (1) lvim lvis cleared (00h) cleared (00h) cleared (00h) held chapter 15 reset function user?s manual u17446ej5v0ud 255 15.1 register for confirming reset source many internal reset generation sources exist in the 78k0s/ kb1+. the reset control flag register (resf) is used to store which source has generated the reset request. resf can be read by an 8-bit memory manipulation instruction. reset signal generation by reset input or power-on-clear (poc) circuit, and reading resf clear resf to 00h. figure 15-5. format of reset control flag register (resf) address: ff54h after reset: 00h note r symbol 7 6 5 4 3 2 1 0 resf 0 0 0 wdtrf 0 0 0 lvirf wdtrf internal reset request by watchdog timer (wdt) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. lvirf internal reset request by low-voltage detector (lvi) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. note the value after reset varies depending on the reset source. caution do not read data by a 1-bi t memory manipulation instruction. the status of resf when a reset request is generated is shown in table 15-2. table 15-2. resf status when reset request is generated reset source flag reset input reset by poc reset by wdt reset by lvi wdtrf set (1) held lvirf cleared (0) cleared (0) held set (1) user?s manual u17446ej5v0ud 256 chapter 16 power-on-clear circuit 16.1 functions of power-on-clear circuit the power-on-clear circuit (poc) has the following functions. ? generates internal reset signal at power on. ? compares supply voltage (v dd ) and detection voltage (v poc = 2.1 v (typ.)), and generates internal reset signal when v dd < v poc . ? compares supply voltage (v dd ) and detection voltage (v poc = 2.1 v (typ.)), and releases internal reset signal when v dd v poc . cautions 1. if an internal reset signal is generated in the poc circui t, the reset control flag register (resf) is cleared to 00h. 2. use these products in th e following voltage range becau se the detection voltage (v poc ) of the poc circuit is the supply voltage range. standard product, (a) grade product: 2.2 to 5.5 v, (a2) grade product: 2.26 to 5.5 v remark this product incorporates multiple hardware functions that generate an internal reset signal. a flag that indicates the reset cause is located in the reset cont rol flag register (resf) for when an internal reset signal is generated by the watchdog timer (wdt) or lo w-voltage-detection (lvi) circuit. resf is not cleared to 00h and the flag is set to 1 when an in ternal reset signal is generated by wdt or lvi. for details of resf, see chapter 15 reset function . chapter 16 power-on-clear circuit user?s manual u17446ej5v0ud 257 16.2 configuration of power-on-clear circuit the block diagram of the power-on-clear circuit is shown in figure 16-1. figure 16-1. block diagram of power-on-clear circuit ? + reference voltage source internal reset signal v dd v dd 16.3 operation of power-on-clear circuit in the power-on-clear circuit, the supply voltage (v dd ) and detection voltage (v poc = 2.1 v (typ.)) are compared, and an internal reset signal is generated when v dd < v poc , and an internal reset is released when v dd v poc . figure 16-2. timing of internal reset si gnal generation in powe r-on-clear circuit time supply voltage (v dd ) poc detection voltage (v poc = 2.1 v (typ.)) internal reset signal chapter 16 power-on-clear circuit user?s manual u17446ej5v0ud 258 16.4 cautions for power-on-clear circuit in a system where the supply voltage (v dd ) fluctuates for a certain period in the vicinity of the poc detection voltage (v poc ), the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the oper ation of the microcontroller can be arbitrarily set by taking the following action. chapter 16 power-on-clear circuit user?s manual u17446ej5v0ud 259 figure 16-3. example of software pr ocessing after release of reset (2/2) ? checking reset cause yes no check reset source power-on-clear/external reset generated reset processing by watchdog timer reset processing by low-voltage detector no wdtrf of resf register = 1? lvirf of resf register = 1? yes user?s manual u17446ej5v0ud 260 chapter 17 low-voltage detector 17.1 functions of low-voltage detector the low-voltage detector (lvi) has following functions. ? compares supply voltage (v dd ) and detection voltage (v lvi ), and generates an internal interrupt signal or internal reset signal when v dd < v lvi . ? detection levels (ten levels) of supply voltage can be changed by software. ? interrupt or reset function can be selected by software. ? operable in stop mode. when the low-voltage detector is used to reset, bit 0 (lvirf) of the reset control flag regi ster (resf) is set to 1 if reset occurs. for deta ils of resf, refer to chapter 15 reset function . 17.2 configuration of low-voltage detector the block diagram of the low-voltage detector is shown in figure 17-1. figure 17-1. block diagram of low-voltage detector lvion reference voltage source n-ch low-voltage detection level select register (lvis) low-voltage detect register (lvim) lvis2 lvimd lvif intlvi internal reset signal 4 lvis1 lvis0 lvis3 low-voltage detection level selector selector internal bus + ? v dd v dd chapter 17 low-voltage detector user?s manual u17446ej5v0ud 261 17.3 registers controlling low-voltage detector the low-voltage detector is contro lled by the following registers. ? low-voltage detect register (lvim) ? low-voltage detection level select register (lvis) (1) low-voltage detect register (lvim) this register sets low-voltag e detection and the operation mode. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h note 1 . figure 17-2. format of low-vol tage detect register (lvim) <0> lvif <1> lvimd 2 0 3 0 4 0 5 0 6 0 <7> lvion symbol lvim address: ff50h after reset: 00h note 1 r/w note 2 lvion note 3 enabling low-voltage detection operation 0 disable operation 1 enable operation lvimd low-voltage detection operation mode selection 0 generate interrupt signal when supply voltage (v dd ) < detection voltage (v lvi ) 1 generate internal reset signal when supply voltage (v dd ) < detection voltage (v lvi ) lvif note 4 low-voltage detection flag 0 supply voltage (v dd ) detection voltage (v lvi ), or when operation is disabled 1 supply voltage (v dd ) < detection voltage (v lvi ) notes 1. retained only after a reset by lvi. 2. bit 0 is a read-only bit. 3. when lvion is set to 1, operation of the com parator in the lvi circuit is started. use software to instigate a wait of at least 0.2 ms from when lvion is set to 1 until the voltage is confirmed at lvif. 4. the value of lvif is output as the interru pt request signal intlvi when lvion = 1 and lvimd = 0. cautions 1. to stop lvi, follow either of the procedures below. ? when using 8-bit manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0. 2. be sure to set bits 2 to 6 to 0. chapter 17 low-voltage detector user?s manual u17446ej5v0ud 262 (2) low-voltage detection l evel select register (lvis) this register selects the low-voltage detection level. this register can be set by an 8-bit memory manipulation instruction. reset signal generation clears this register to 00h note . figure 17-3. format of low-voltage dete ction level select register (lvis) address: ff51h, after reset: 00h note r/w symbol 7 6 5 4 3 2 1 0 lvis 0 0 0 0 lvis3 lvis2 lvis1 lvis0 lvis3 lvis2 lvis1 lvis0 detection level 0 0 0 0 v lvi0 (4.3 v 0.2 v) 0 0 0 1 v lvi1 (4.1 v 0.2 v) 0 0 1 0 v lvi2 (3.9 v 0.2 v) 0 0 1 1 v lvi3 (3.7 v 0.2 v) 0 1 0 0 v lvi4 (3.5 v 0.2 v) 0 1 0 1 v lvi5 (3.3 v 0.15 v) 0 1 1 0 v lvi6 (3.1 v 0.15 v) 0 1 1 1 v lvi7 (2.85 v 0.15 v) 1 0 0 0 v lvi8 (2.6 v 0.1 v) 1 0 0 1 v lvi9 (2.35 v 0.1 v) other than above setting prohibited note retained only after a reset by lvi. cautions 1. bits 4 to 7 must be set to 0. 2. if values other than same values are written during lvi operation, the value becomes undefined at the very moment it is written, and thus be sure to stop lvi (bit 7 of lvim register (lvion) = 0) before writing. chapter 17 low-voltage detector user?s manual u17446ej5v0ud 263 17.4 operation of low-voltage detector the low-voltage detector can be us ed in the following two modes. ? used as reset compares the supply voltage (v dd ) and detection voltage (v lvi ), and generates an internal reset signal when v dd < v lvi , and releases internal reset when v dd v lvi . ? used as interrupt compares the supply voltage (v dd ) and detection voltage (v lvi ), and generates an interrupt signal (intlvi) when v dd < v lvi . the operation is set as follows. (1) when used as reset ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set the detection voltage using bits 3 to 0 (lvis3 to lvis0) of the low-voltage detection level select register (lvis). <3> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <4> use software to instigate a wait of at least 0.2 ms. <5> wait until ?supply voltage (v dd ) detection voltage (v lvi )? at bit 0 (lvif) of lvim is confirmed. <6> set bit 1 (lvimd) of lvim to 1 (generates internal reset signal when supply voltage (v dd ) < detection voltage (v lvi )). figure 17-4 shows the timing of generating the internal reset signal of the low-voltage detector. numbers <1> to <6> in this figure correspond to <1> to <6> above. cautions 1. <1> must always be executed. when lvimk = 0, an interrupt may occur immediately after the processing in <3>. 2. if supply voltage (v dd ) detection voltage (v lvi ) when lvim is set to 1, an internal reset signal is not generated. ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvimd to 0 and lvion to 0 in that order. chapter 17 low-voltage detector user?s manual u17446ej5v0ud 264 figure 17-4. timing of low-voltage dete ctor internal reset signal generation <2> <1> note 1 note 2 <3> <5> <6> h supply voltage (v dd ) lvi detection voltage (v lvi ) poc detection voltage (v poc ) lvif flag lvirf flag note 3 lvi reset signal poc reset signal internal reset signal lvimk flag (set by software) lvion flag (set by software) lvimd flag (set by software) cleared by software not cleared not cleared not cleared not cleared cleared by software time clear clear clear <4> 0.2 ms or longer notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the lvif flag may be set (1). 3. lvirf is bit 0 of the reset control flag regi ster (resf). for details of resf, refer to chapter 15 reset function . remark <1> to <6> in figure 17-4 above correspond to <1> to <6> in the description of ?when starting operation? in 17.4 (1) when used as reset . chapter 17 low-voltage detector user?s manual u17446ej5v0ud 265 (2) when used as interrupt ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set the detection voltage using bits 3 to 0 (lvis3 to lvis0) of the low-voltage detection level select register (lvis). <3> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <4> use software to instigate a wait of at least 0.2 ms. <5> wait until ?supply voltage (v dd ) detection voltage (v lvi )? at bit 0 (lvif) of lvim is confirmed. <6> clear the interrupt request flag of lvi (lviif) to 0. <7> release the interrupt mask flag of lvi (lvimk). <8> execute the ei instruction (w hen vector interrupts are used). figure 17-5 shows the timing of generat ing the interrupt signal of the low- voltage detector. numbers <1> to <7> in this figure correspond to <1> to <7> above. ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0. figure 17-5. timing of low-voltage detector interrupt signal generation <2> <1> note 1 <3> <5> note 2 note 2 supply voltage (v dd ) lvi detection voltage (v lvi ) poc detection voltage (v poc ) lvif flag intlvi lviif flag internal reset signal lvimk flag (set by software) lvion flag (set by software) time <6> cleared by software <7> cleared by software <4> 0.2 ms or longer note 2 notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. an interrupt request signal (intlvi) may be generat ed, and the lvif and lviif flags may be set to 1. remark <1> to <7> in figure 17-5 above correspond to <1> to <7> in the description of ?when starting operation? in 17.4 (2) when used as interrupt . chapter 17 low-voltage detector user?s manual u17446ej5v0ud 266 17.5 cautions for low-voltage detector in a system where the supply voltage (v dd ) fluctuates for a certain period in t he vicinity of the lvi detection voltage (v lvi ), the operation is as follows depending on how the low-voltage detector is used. <1> when used as reset the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the star t of the operation of the microcontroller can be arbitrarily set by taking action (1) below. <2> when used as interrupt interrupt requests may be frequently generated. take (b) of action (2) below. in this system, take the following actions. chapter 17 low-voltage detector user?s manual u17446ej5v0ud 267 figure 17-6. example of software pr ocessing after release of reset (1/2) ? if supply voltage fluctuation is 50 ms or less in vicinity of lvi detection voltage yes no setting lvi detection voltage or more (lvif = 0 ?) yes lvif = 0 restarting the timer h1 (tmhe1 = 0 tmhe1 = 1) no lvi reset ; check reset source note initialization of ports setting wdt reset initialization processing <1> setting 8-bit timer h1 (50 ms is measured) source: f xp (2.1 mhz (max.))/2 12 , 51 ms when the compare value is 25 timer starts (tmhe1 = 1) clears wdt 50 ms has passed? (tmifh1 = 1?) initialization processing <2> ; setting the division ratio of the system clock, timer, a/d converter, etc. the low-voltage detector is operated (lvion = 1) ; the detection level is set with lvis. ; clear low-voltage detection flag. ; clear timer counter and timer starts. ; f xp = high-speed internal oscillation clock (8.4 mhz (max.))/2 2 (default value) note a flowchart is shown on the next page. chapter 17 low-voltage detector user?s manual u17446ej5v0ud 268 figure 17-6. example of software pr ocessing after release of reset (2/2) ? checking reset source yes no yes no check reset source power-on-clear/external reset generated reset processing by watchdog timer reset processing by low-voltage detector wdtrf of resf register = 1? lvirf of resf register = 1? user?s manual u17446ej5v0ud 269 chapter 18 option byte 18.1 functions of option byte the address 0080h of the flash memory of the 78k0s/kb1+ is an option byte area. when power is supplied or when starting after a reset, the option byte is automatical ly referenced, and settings for the specified functions are performed. when using the product, be sure to set the following functions by using the option byte. (1) selection of system clock source ? high-speed internal oscillation clock ? crystal/ceramic oscillation clock ? external clock input (2) low-speed internal oscillation clock oscillation ? cannot be stopped. ? can be stopped by software. (3) control of reset pin ? used as reset pin ? reset pin is used as an input port pin (p34) (refer to 18.3 caution when the reset pin is used as an input-only port pin (p34) ). (4) oscillation stabilization time on po wer application or after reset release ? 2 10 /f x ? 2 12 /f x ? 2 15 /f x ? 2 17 /f x figure 18-1. positioning of option byte option byte oscsel1 rmce 1 1 flash memory (4096/8192 8 bits) 0fffh/1fffh 0000h 0080h def osts1 oscsel0 def osts0 liocp chapter 18 option byte user?s manual u17446ej5v0ud 270 18.2 format of option byte format of option bytes is shown below. figure 18-2. format of option byte (1/2) address: 0080h 7 6 5 4 3 2 1 0 1 defosts1 defosts0 1 rmce oscsel1 oscsel0 liocp defosts1 defosts0 oscillation stabilization time on power application or after reset release 0 0 2 10 /fx (102.4 s) 0 1 2 12 /fx (409.6 s) 1 0 2 15 /fx (3.27 ms) 1 1 2 17 /fx (13.1 ms) caution the setting of this option is valid only wh en the crystal/ceramic oscillation clock is selected as the system clock source. no wait time elapses if the high- speed internal oscillation clock or external clock input is select ed as the system clock source. rmce control of reset pin 1 reset pin is used as is. 0 reset pin is used as input port pin (p34). caution because the option byte is re ferenced after reset release, if a low level is input to the reset pin before the option byte is referenced , then the reset state is not released. also, when setting 0 to rmce, connect the pull-up resistor. oscsel1 oscsel0 selection of system clock source 0 0 crystal/ceramic oscillation clock 0 1 external clock input 1 high-speed internal oscillation clock caution because the x1 and x2 pins are also used as the p121 and p122 pins, the conditions under which the x1 and x2 pins can be used differ depending on the selected system clock source. (1) crystal/ceramic oscilla tion clock is selected the x1 and x2 pins cannot be used as i/o port pins because they are used as clock input pins. (2) external clock input is selected because the x1 pin is used as an external clock input pin, p121 cannot be used as an i/o port pin. (3) high-speed internal oscillation clock is selected p121 and p122 can be used as i/o port pins. remark : don?t care chapter 18 option byte user?s manual u17446ej5v0ud 271 figure 18-2. format of option byte (2/2) liocp low-speed internal oscillates 1 cannot be stopped (oscillation does not stop even if 1 is written to the lsrstop bit) 0 can be stopped by software (oscillation stops when 1 is written to the lsrstop bit) cautions 1. if it is selected that low-speed intern al oscillator cannot be stopped, the count clock to the watchdog timer (wdt) is fixed to lo w-speed internal oscillation clock. 2. if it is selected that low-speed internal oscillator can be stopped by software, supply of the count clock to wdt is stopped in the hal t/stop mode, regardless of the setting of bit 0 (lsrstop) of the low-speed internal osc illation mode register (lsrcm). similarly, clock supply is also stopped when a clock othe r than the low-speed internal oscillation clock is selected as a count clock to wdt. while the low-speed internal oscillator is operating (lsrstop = 0), the clock can be supplied to the 8-bit timer h1 even in the stop mode. remarks 1. ( ): f x = 10 mhz 2. for the oscillation stabilization time of the resonat or, refer to the characteristics of the resonator to be used. 3. an example of software coding for setting the option bytes is shown below. opb oseg at 0080h db 10010001b ; set to option byte ; low-speed internal oscillator cannot be stopped ; the system clock is a crystal or ceramic resonator. ; the reset pin is used as an input-only port pin (p34). ; minimum oscillation stabilization time ( 2 10 /f x ) 4. for details on the timing at which the option byte is referenced, see chapter 15 reset function . 18.3 caution when the reset pin is used as an input-only port pin (p34) be aware of the following when re-erasing/-writing (b y on-board programming using a dedicated flash memory programmer) an already-written device which has been set as ?the reset pin is used as an input-only port pin (p34)? by the option byte function. before supplying power to the target system, connect a dedi cated flash memory programmer and turn its power on. if the power is supplied to the tar get system beforehand, the flash memo ry programming mode cannot be switched to. user?s manual u17446ej5v0ud 272 chapter 19 flash memory 19.1 features the internal flash memory of the 78k0s/kb1+ has the following features. { erase/write even without preparing a separate dedicated power supply { capacity: 4 kb/8 kb ? erase unit: 1 block (256 bytes) ? write unit: 1 block (at on-board/off-board programming time), 1 byte (at self programming time) { rewriting method ? rewriting by communication with dedicated flash memory programmer (on-board/off-board programming) ? rewriting flash memory by user program (self programming) { supports rewriting of the flash memory at on-board/ off-board programming time through security functions { supports security functions in block units at self programming time through protect bytes chapter 19 flash memory user?s manual u17446ej5v0ud 273 19.2 memory configuration the 4/8 kb internal flash memory area is divided into 16/32 blocks and can be programmed/erased in block units. all the blocks can also be erased at once, by using a dedicated flash memory programmer. figure 19-1. flash memory mapping special function resister (256 bytes) internal high-speed ram (256 bytes) use prohibited flash memory (4/8 kb) ffffh ff00h feffh fe00h fdffh 0000h 0000h 0100h 00ffh block 0 (256 bytes) block 1 (256 bytes) block 2 (256 bytes) block 13 (256 bytes) block 14 (256 bytes) block 15 (256 bytes) block 0 (256 bytes) block 1 (256 bytes) block 2 (256 bytes) block 13 (256 bytes) block 14 (256 bytes) block 15 (256 bytes) block 29 (256 bytes) block 30 (256 bytes) block 31 (256 bytes) 4 kb 8 kb 0200h 01ffh 0300h 02ffh 0d00h 0cffh 0e00h 0dffh 0f00h 0effh 1000h 0fffh 1d00h 1cffh 1e00h 1dffh 1f00h 1effh 1fffh ? pd78f9232 ? pd78f9234 19.3 functional outline the internal flash memory of the 78k0s/kb1+ can be rewrit ten by using the rewrite function of the dedicated flash memory programmer, regardless of whet her the 78k0s/kb1+ has already been mounted on th e target system or not (on-board/off-board programming). the function for rewriting a program with the user prog ram (self programming), which is ideal for an application when it is assumed that the program is changed after pr oduction/shipment of the target system, is provided. refer to table 19-1 for the flash memory writing control function. in addition, a security function that prohi bits rewriting the user program written to the internal flash memory is also supported, so that the program c annot be changed by an unauthorized person. refer to 19.7.3 security settings for details on the security function. chapter 19 flash memory user?s manual u17446ej5v0ud 274 table 19-1. rewrite method rewrite method functional outline operation mode on-board programming flash memory can be rewritten after the device is mounted on the target system, by using a dedicated flash memory programmer. off-board programming flash memory can be rewritten before the device is mounted on the target system, by using a dedicated flash memory programmer and a dedicated program adapter board (fa series). flash memory programming mode self programming flash memory can be rewritten by executing a user program that has been written to the flash memory in advance by means of on-board/off- board programming. self programming mode remarks 1. the fa series is a product of na ito densei machida mfg. co., ltd. 2. refer to the following sections for details on the flash memory writing control function. ? 19.7 on-board and off-board flash memory programming ? 19.8 flash memory programming by self programming 19.4 writing with flash memory programmer the following two types of dedicated flash memory programmers can be used for writing data to the internal flash memory of the 78k0s/kb1+. ? flashpro5 (pg-fp5, fl-pr5) ? qb-mini2 data can be written to the flash memory on-board or o ff-board, by using a dedicated flash memory programmer. (1) on-board programming the contents of the flash memory can be rewritten after the 78k0s/kb1+ has been mounted on the target system. the connectors that connect the dedicated flash memory programmer and the test pad must be mounted on the target system. the test pad is require d only when writing data with the crystal/ceramic resonator mounted (refer to figure 19-4 for mounting of the test pad). (2) off-board programming data can be written to the flash memory with a dedica ted program adapter (fa se ries) before the 78k0s/kb1+ is mounted on the target system. remark the fl-pr5 and fa series are products of naito densei machida mfg. co., ltd. chapter 19 flash memory user?s manual u17446ej5v0ud 275 19.5 programming environment the environment required for writing a program to the flash memory is illustrated below. figure 19-2. environment for writing prog ram to flash memory (flashpro5/qb-mini2) rs-232-c usb host machine reset clk so/txd dedicated flash memory programmer flashpro5 qb-mini2 v dd v ss 78k0s/kb1+ remark for qb-mini2, the name of the so/txd signal is data. a host machine that controls the ded icated flash memory programmer is nec essary. when using the pg-fp5 or fl-pr5, data can be written with just t he dedicated flash memory programmer after downloading the program from the host machine. uart is used for manipulation such as writing and erasing when interfacing between the dedicated flash memory programmer and the 78k0s/kb1+. to write the flash memory off-board, a dedicated program adapter (fa series) is necessary. download the latest firmware for flash memory progr ammer, programming gui, and parameter file from the download site for development tools (http://www.necel.com/micro/en/ods/). chapter 19 flash memory user?s manual u17446ej5v0ud 276 table 19-2. wiring between 78k 0s/kb1+ and flashpro5/qb-mini2 flashpro5/qb-mini2 connecti on pin 78k0s/kb1+ connection pin pin name i/o pin function pin name clk output clock to 78k0s/kb1+ x1/p121 so/txd output receive si gnal/on-board mode signal x2/p122 /reset output reset signal reset/p34 v dd ? v dd voltage generation/voltage monitor gnd ? ground v dd v ss figure 19-3. communication with flashpro5/qb-mini2 (30-pin products) clk so/txd /reset gnd flashpro5/ qb-mini2 signal name 78k0s/kb1+ v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 remark for qb-mini2, the name of the so/txd signal is data. chapter 19 flash memory user?s manual u17446ej5v0ud 277 19.6 pin connection on board to write the flash memory on-board, connectors that connect the dedicat ed flash memory programmer must be provided on the target system. first provide a function that selects the normal operation mode or flash memory programming mode on the board. when the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after re set. therefore, if the external device does not recognize the state immediately after reset, the pins must be processed as described below. the state of the pins in the se lf programming mode is the same as that in the halt mode. 19.6.1 x1 and x2 pins the x1 and x2 pins are used as the se rial interface of flash memory progra mming. therefore, if the x1 and x2 pins are connected to an external devic e, a signal conflict occurs. to prev ent the conflict of signals, isolate the connection with the external device. similarly, when a capacitor is connected to the x1 and x2 pins, the waveform during communication is changed, and thus communication may be disabled depending on the capacitor capacitance. ma ke sure to isolate the connection with the capacitor during flash programming. perform the following processing (1) and (2) when on-board programming is performed with the resonator mounted, when it is difficult to isolate the resonator, while a cryst al or ceramic resonator is selected as the system clock. (1) mount the minimum-possible test pads between the devi ce and the resonator, and connect the programmer via the test pad. keep the wiring as short as possible (refer to figure 19-4 and table 19-3 ). (2) set the oscillation frequency of the communication clock for writing using the programming gui of the dedicated flash memory programmer. research the seri es/parallel resonant and antiresonant frequencies of the resonator used, and set the oscillation frequency so that it is outside the ran ge of the resonant frequency 10% (refer to figure 19-5 and table 19-4 ). figure 19-4. example of mounting test pads x2 x1 v ss test pad table 19-3. clock to be used and mounting of test pads clock to be used mounting of test pads high-speed internal oscillation clock external clock before resonator is mounted not required crystal/ceramic oscillation clock after resonator is mounted required chapter 19 flash memory user?s manual u17446ej5v0ud 278 set oscillation fre q uenc y click figure 19-5. pg-fp5 programming gui setting example table 19-4. oscillation frequency and pg -fp5 programming gui setting value example oscillation frequency pg-fp5 programming gui setting value example (communication frequency) 2 mhz f x < 4 mhz 8 mhz 4 mhz f x < 8 mhz 9 mhz 8 mhz f x < 9 mhz 10 mhz 9 mhz f x 10 mhz 8 mhz caution the above values are recommended valu es. depending on the usage environment these values may change, so set them after having performed sufficient evaluations. 19.6.2 reset pin if the reset signal of the dedicated flash memory programm er is connected to the reset pin that is connected to the reset signal generator on the board, signal collision takes pl ace. to prevent this co llision, isolate the connection with the reset signal generator. if the reset signal is input from the user system whil e the flash memory programming mode is set, the flash memory will not be correctly programmed. do not input any signal other than the reset signal of the dedicated flash memory programmer. (main window) (standard tab in device setup window) chapter 19 flash memory user?s manual u17446ej5v0ud 279 figure 19-6. signal collision (reset pin) reset dedicated flash memory programmer connection signal reset signal generator signal collision output pin in the flash memory programming mode, the signal output by the reset signal generator collides with the signal output by the dedicated flash memory programmer. therefore, isolate the signal of the reset signal generator. 78k0s/kb1+ 19.6.3 port pins when the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately after reset. if exter nal devices connected to the ports do not recognize the port status immediately after reset, the port pin must be connected to v dd or v ss via a resistor. the state of the pins in the se lf programming mode is the same as that in the halt mode. 19.6.4 power supply connect the v dd pin to v dd of the flash memory programmer, and the v ss pin to v ss of the flash memory programmer. supply the same other power supplies (av ref and av ss ) as those in the normal operation mode. chapter 19 flash memory user?s manual u17446ej5v0ud 280 19.7 on-board and off-board flash memory programming 19.7.1 flash memory programming mode to rewrite the contents of the fl ash memory by using the dedicated flash memory programmer, set the 78k0s/kb1+ in the flash memory programming mode. w hen the 78k0s/kb1+ is connected to the flash memory programmer and a communication command is transmitted to the mi crocontroller, the microcontroller is set in the flash memory programming mode. change the mode by using a jumper when writing the flash memory on-board. 19.7.2 communication commands the dedicated flash memory programmer controls the 78k 0s/kb1+ by using commands. the signals sent from the dedicated flash memory programmer to the 78k0s/kb1+ are called communication commands, and the commands sent from the 78k0s/kb1+ to the dedicat ed flash memory programmer are called response. figure 19-7. communication commands 78k0s/kb1+ dedicated flash memory programmer communication command response flashpro5 minicube2 qb-mini2 communication commands are listed in the table below. all these communication commands are issued from the flash memory programmer and the 78k0s/kb1+ performs proc essing corresponding to the respective communication commands. table 19-5. communication commands classification command name function batch erase (chip erase) command erases the contents of the entire memory erase block erase command erases the contents of the memory of the specified block write write command writes to the specified address range and executes a verify check of the contents. checksum checksum command reads the checksum of the specified address range and compares with the written data. blank check blank check command confirms t he erasure status of the entire memory. security security setting command prohibits batch erase (chip erase) command, block erase command, and write command to prevent operation by third parties. the 78k0s/kb1+ returns a response for the communi cation command issued by the dedicated flash memory programmer. the response names sent from the 78k0s/kb1+ are listed below. chapter 19 flash memory user?s manual u17446ej5v0ud 281 table 19-6. response name response name function ack acknowledges command/data. nak acknowledges illegal command/data. 19.7.3 security settings the operations shown below can be prohibi ted using the security setting command. ? batch erase (chip erase) is prohibited execution of the block erase and batch erase (chip eras e) commands for entire blocks in the flash memory is prohibited. once execution of the batch erase (chip erase) command is prohibited, all the prohibition settings can no longer be cancelled. caution after the security setting of the batch erase is set, erasure cannot be performed for the device. in addition, even if a write command is executed, data different from that which has already been written to the flash memory cannot be written because the erase command is disabled. ? block erase is prohibited execution of the block erase command in the flash me mory is prohibited. this prohibition setting can be cancelled using the batch erase (chip erase) command. ? write is prohibited execution of the write and block erase commands for enti re blocks in the flash memory is prohibited. this prohibition setting can be cancelled using the batch erase (chip erase) command. remark the security setting is valid when the programming mode is set next time. the batch erase (chip erase), block erase, and write commands are enabled by the default setting when the flash memory is shipped. the above security settings are possibl e only for on-board/off-board programming. each security setting can be used in combination. table 19-7 shows the relationship between the erase and write commands when the 78k0s/kb1+ security function is enabled. table 19-7. relationship between comma nds when security function is enabled command security batch erase (chip erase) command block erase command write command when batch erase (chip erase) security operation is enabled disabled enabled note when block erase security operation is enabled enabled when write security operation is enabled enabled disabled disabled note since the erase command is disabled, data different from that which has already been written to the flash memory cannot be written. chapter 19 flash memory user?s manual u17446ej5v0ud 282 table 19-8 shows the relationship between the securi ty setting and the operation in each programming mode. table 19-8. relationship between security se tting and operation in each programming mode on-board/off-board programming self programming programming mode security setting security setting security operation security setting security operation batch erase (chip erase) block erase write possible valid note 1 impossible invalid note 2 notes 1. execution of each command is prohi bited by the security setting. 2. execution of self programming command is possible regardless of the security setting. 19.8 flash memory programming by self programming the 78k0s/kb1+ supports a self progra mming function that can be used to rewrite the flash memory via a user program, making it possible to upgrade programs in the field. caution self programming processing must be in cluded in the program before performing self programming. remarks 1. for usage of self programming, refer to the examples from 19.8.4 onward. 2. to use the internal flash memory of the 78k0s/ kb1+ as the external eeprom for storing data, refer to 78k0s/kx1+ eeprom emulation application note (u17379e) . 19.8.1 outline of self programming to execute self programming, shift the mode from the nor mal operation of the user pr ogram (normal mode) to the self programming mode. write/erase processing for the flash memory, which has been set to the register in advance, is performed by executing the halt instruction during se lf programming mode. the ha lt state is automatically released when processing is completed. to shift to the self programming mode, execute a s pecific sequence for a specific register. refer to 19.8.4 example of shifting normal mode to self programming mode for details. remark data written by self programming can be referenced with the mov instruction. table 19-9. self programming mode mode user program execution execution of write/erase for flash memory with halt instruction normal mode enabled ? self programming mode enabled note enabled note maskable interrupt servicing is disabled during self programming mode. figure 19-8 shows a block diagram for self programming, figure 19-9 shows the self programming state transition diagram, table 19-10 lists the commands for controlling self programming. chapter 19 flash memory user?s manual u17446ej5v0ud 283 flash programming mode control register (flpmc) flash protect command register (pfcmd) self programming mode setting register self programming mode setting sequencer halt signal self programming command execution flash memory controller verify circuit write circuit erase circuit weprerr vcerr fprerr halt release signal flcmd2 flcmd1 flcmd0 internal bus flash programming command register (flcmd) increment circuit flash memory protect byte prself4 prself3 prself2 prself1 prself0 5 flash address pointer h (flaph) flash address pointer l (flapl) flash address pointer h compare register (flaphc) matched matched flash address pointer l compare register (flaplc) flash write buffer register (flw) not matched internal bus flash status register (pfs) 3 figure 19-8. block diagram of self programming chapter 19 flash memory user?s manual u17446ej5v0ud 284 figure 19-9. self programming state transition diagram register for self programming self programming mode self programming command under execution normal mode user program operation setting operation reference flash memory flash memory control block (hardware) specific sequence self programming command completion/error self programming command execution by halt instruction operation setting table 19-10. self programming controlling commands command name function time taken from halt instruction execution to command execution end internal verify 1 this command is used to check if data has been correctly written to the flash memory. it is used to check whether data has been written to an entire block. internal verify for 1 block (internal verify command executed once): 6.8 ms internal verify 2 this command is used to check if data has been correctly written to the flash memory. it is used to check whether data has been written to multiple addresses in the same block. internal verify of 1 byte: 27 s block erasure note this command is used to erase a specified block. specify the block number before execution. 8.5 ms block blank check this command is used to check if data in a specified block has been erased. specify the block number, then execute this command. 480 s byte write this command is used to write 1-byte data to the specified address in the flash memory. specify the write address and write data, then execute this command. 150 s note set the number of retrials larger than the block erasur e time divided by the time (8.5 ms) for one erase, in accordance with the time (max. value) required for flash memory block erasures. remark the internal verify 1 command can be executed by specifying an address in the same block, but internal verify 2 command is recommended if data is writt en to multiple addresses in the same block. chapter 19 flash memory user?s manual u17446ej5v0ud 285 19.8.2 cautions on self programming function ? no instructions can be executed while a self programming command is being executed. therefore, clear and restart the watchdog timer counter in advance so that the watchdog timer does not overflow during self programming. refer to table 19-10 for the time taken for the execution of self programming. ? interrupts that occur during self programming can be ac knowledged after self programming mode ends. to avoid this operation, disable interrupt servicing (by setti ng mk0 and mk1 to ffh, and exec uting the di instruction) when shifting from the normal mode to the self programming mode with a specific sequence. ? ram is not used while a self programming command is being executed. ? if the supply voltage drops or the reset signal is input while the flash memory is being written or erased, writing/erasing is not guaranteed. ? the value of the blank data set during block erasure is ffh. ? set the cpu clock beforehand so that it is 1 mhz or higher during self programming. ? execute self programming after executing the nop and halt instructions immediately after executing a specific sequence to set self programming mode. at this time, the halt instruction is autom atically released after 10 s (max.) + 2 cpu clocks (f cpu ). ? if the clock of the oscillator or an external clock is selected as the system clock, execute the nop and halt instructions immediately after executing a specific sequence to set self programming mode, wait for 8 s after releasing the halt status, and then execute self programming. ? check fprerr using a 1-bit memory manipulation instruction. ? the state of the pins in self programming mode is the same as that in halt mode. ? since the security function set via on-board/off-board programming is disabled in self programming mode, the self programming command can be executed regardless of the se curity function setting. to disable write or erase processing during self programming, set the protect byte. ? be sure to clear bits 5 to 7 of flash address point er h (flaph) and flash address pointer h compare register (flaphc) to 0 before executing the se lf programming command. if the se lf programming command is executed with these bits set to 1, the device may malfunction. ? clear the value of the flcmd register to 00h immediat ely before setting to self programming mode and normal mode. 19.8.3 registers used for self programming function the following registers are used fo r the self programming function. ? flash programming mode control register (flpmc) ? flash protect command register (pfcmd) ? flash status register (pfs) ? flash programming command register (flcmd) ? flash address pointers h and l (flaph and flapl) ? flash address pointer h compare register and flash ad dress pointer l compare register (flaphc and flaplc) ? flash write buffer register (flw) the 78k0s/kb1+ has an area called a protect by te at address 0081h of the flash memory. chapter 19 flash memory user?s manual u17446ej5v0ud 286 (1) flash programming mode control register (flpmc) this register is used to set the operation mode when data is written to the flash memory in the self programming mode, and to read the set value of the protect byte. data can be written to flpmc only in a specific sequence (refer to 19.8.3 (2) flash protect command register (pfcmd) ) so that the application system does not st op by accident because of malfunctions due to noise or program hang-ups. this register is set with an 8-bit memory manipulation instruction. reset signal generation makes the c ontents of this register undefined. figure 19-10. format of flash progra mming mode control register (flpmc) address: ffa2h after reset: undefined note 1 r/w note 2 symbol 7 6 5 4 3 2 1 0 flpmc 0 prself4 prself3 prself2 prself1 prself0 0 flspm flspm selection of operation mode during self programming mode 0 normal mode this is the normal operation status. executing the halt instruction sets standby status. 1 self programming mode self programming commands can be ex ecuted by executing the specific sequence to change modes while in normal mode. set a command, an address, and data to be written, then execute the halt instruction to execute self programming. prself4 prself3 prself2 prself1 prself0 the set value of the protect byte is read to these bits. notes 1. bit 0 (flspm) is cleared to 0 when reset is released. the set value of the protect byte is read to bits 2 to 6 (prself0 to prself4) after reset is released. 2. bits 2 to 6 (prself0 to prself4) are read-only. cautions 1. cautions in the case of setting the self programming mode, refer to 19.8.2 cautions on self programming function. 2. set the cpu clock beforehand so that it is 1 mhz or higher during self programming. 3. execute self programming after executing the nop and halt instructions immediately after executing a specifi c sequence to set self programming mode. at this time, the halt instruct ion is automatically released after 10 s (max.) + 2 cpu clocks (f cpu ). 4. if the clock of the oscillator or an external clock is selected as the system clock, execute the nop and halt instru ctions immediately after executing a specific sequence to set self programming mode, wait for 8 s after releasing the halt status, and then execute self programming. 5. clear the value of the flcmd regist er to 00h immediately before setting to self programming mode and normal mode. chapter 19 flash memory user?s manual u17446ej5v0ud 287 (2) flash protect command register (pfcmd) if the application system stops inadver tently due to malfunction caused by noise or program hang-up, an operation to write the flash programming mode control register (flpmc) may have a serious effect on the system. pfcmd is used to protect flpmc from being wr itten, so that the applic ation system does not stop inadvertently. writing flpmc is enabled only when a write operation is performed in the following specific sequence. <1> write a specific value to pfcmd (a5h) <2> write the value to be set to bit 0 (flspm) of the flpmc (writing in this step is invalid) <3> write the inverted value of the value to be set to bit 0 (flspm) of the flpmc (writing in this step is invalid) <4> write the value to be set to bit 0 (flspm) of the flpmc (writing in this step is valid) caution interrupt servicing cannot be executed in self programming mode. disable interrupt servicing (by executing the di instruction wh ile mk0 and mk1 = ffh) between the points before executing the specific sequence that sets self programming mode and after executing the specific sequence th at changes the mode to the normal mode. this rewrites the value of the register, so that the register cannot be written illegally. occurrence of an illegal write operation can be checked by bit 0 (fprerr) of the flash status register (pfs). a5h must be written to pfcmd each time the value of flpmc is changed. check fprerr using a 1-bit memory manipulation instruction. pfcmd can be set with an 8-bit memory manipulation instruction. reset signal generation makes pfcmd undefined. figure 19-11. format of flash protect command register (pfcmd) address: ffa0h after reset: undefined w symbol 7 6 5 4 3 2 1 0 pfcmd reg7 reg6 reg5 reg4 reg3 reg2 reg1 reg0 (3) flash status register (pfs) if data is not written to the flash programming mode control register (flpmc), which is protected, in the correct sequence (writing the flash protect command register (pfcmd)), flpmc is not written and a protection error occurs. if this happens, bit 0 of pfs (fprerr) is set to 1. when fprerr is 1, it can be cleared to 0 by writing 0 to it. errors that may occur during self programming are refl ected in bit 1 (vcerr) and bit 2 (weprerr) of pfs. vcerr or weprerr can be cleared by writing 0 to them. all the flags of the pfs register mu st be pre-cleared to 0 to check if the operation is performed correctly. pfs can be set with a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears pfs to 00h. caution check fprerr using a 1-bit memory manipulation instruction. chapter 19 flash memory user?s manual u17446ej5v0ud 288 figure 19-12. format of flash status register (pfs) address: ffa1h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pfs 0 0 0 0 0 weprerr vcerr fprerr 1. operating conditions of fprerr flag chapter 19 flash memory user?s manual u17446ej5v0ud 289 (4) flash programming command register (flcmd) this register is used to specify whethe r the flash memory is erased, written, or verified in the self programming mode. this register is set with a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 19-13. format of flash pr ogramming command register (flcmd) address: ffa3h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 flcmd 0 0 0 0 0 flcmd2 flcmd1 flcmd0 flcmd2 flcmd1 flcmd0 command name function 0 0 1 internal verify 1 this command is used to check if data has been correctly written to the flash memory. it is used to check whether data has been written to an entire block. if an error occurs, bit 1 (vcerr) or bit 2 (weprerr) of the flash status register (pfs) is set to 1. 0 1 0 internal verify 2 this command is used to check if data has been correctly written to the flash memory. it is used to check whether data has been written to multiple addresses in the same block. if an error occurs, bit 1 (vcerr) or bit 2 (weprerr) of the flash status register (pfs) is set to 1. 0 1 1 block erase this command is used to erase specified block. it is used both in the on-board mode and self programming mode. 1 0 0 block blank check this command is used to check if the specified block has been erased. 1 0 1 byte write this command is used to write 1-byte data to the specified address in the flash memory. specify the write address and write data, then execute this command. if 1 is written to a bit that has not been erased (a bit for which the data is 0), then bit 2 (weprerr) of the flash status register (pfs) becomes 1. other than above note setting prohibited note if any command other than those above is ex ecuted, command execution may immediately be terminated, and bits 1 and 2 (weprerr and vcerr) of the flash status register (pfs) may be set to 1. chapter 19 flash memory user?s manual u17446ej5v0ud 290 (5) flash address pointers h and l (flaph and flapl) these registers are used to specify the start address of the flash memory when the memory is erased, written, or verified in the self programming mode. flaph and flapl consist of counters, and they ar e incremented until the values match with those of flaphc and flaplc when the programming command is not executed. when the programming command is executed, therefore, set the value again. these registers are set with a 1-bit or 8-bit memory manipulation instruction. reset signal generation makes these registers undefined. figure 19-14. format of flash a ddress pointers h/l (flaph/flapl) address: ffa4h, ffa5h after reset: undefined r/w flaph (ffa5h) flapl (ffa4h) 0 0 0 fla p12 fla p11 fla p10 fla p9 fla p8 fla p7 fla p6 fla p5 fla p4 fla p3 fla p2 fla p1 fla p0 caution be sure to clear bits 5 to 7 of flaph and flaphc to 0 before executing the self programming command. if the self programmi ng command is executed with these bits set to 1, the device may malfunction. (6) flash address pointer h compare register and fl ash address pointer l compare register (flaphc and flaplc) these registers are used to specify the address range in which the intern al sequencer operates when the flash memory is verified in the self programming mode. set flaphc to the same value as that of flaph. set t he last address of the range in which verification is to be executed to flaplc. these registers are set with a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. figure 19-15. format of flash address pointe r h/l compare registers (flaphc/flaplc) address: ffa6h, ffa7h after reset: 00h r/w flaphc (ffa7h) flaplc (ffa6h) 0 0 0 flap c12 flap c11 flap c10 flap c9 flap c8 flap c7 flap c6 flap c5 flap c4 flap c3 flap c2 flap c1 flap c0 cautions 1. be sure to clear bits 5 to 7 of flaph and flaphc to 0 before executing the self programming command. if the self programming command is executed with these bits set to 1, the device may malfunction. 2. set the number of the block subject to a block erase, verify, or blank check (same value as flaph) to flaphc. 3. clear flaplc to 00h when a block erase is performed, and ffh when a blank check is performed. chapter 19 flash memory user?s manual u17446ej5v0ud 291 (7) flash write buffer register (flw) this register is used to store the dat a to be written to the flash memory. this register is set with a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. figure 19-16. format of flash write buffer register (flw) address: ffa8h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 flw flw7 flw6 flw5 flw4 flw3 flw2 flw1 flw0 (8) protect byte this protect byte is used to specify t he area that is to be protec ted from writing or erasin g. the specified area is valid only in the self programming mode. because se lf programming of the protected area is invalid, the data written to the protect ed area is guaranteed. figure 19-17. format of protect byte (1/2) address: 0081h 7 6 5 4 3 2 1 0 1 prself4 prself3 prself2 prself1 prself0 1 1 ? pd78f9232 prself4 prself3 prself2 prself1 prself0 status 0 1 0 0 0 blocks 15 to 0 are protected. 0 1 0 0 1 blocks 13 to 0 are protected. blocks 14 and 15 can be written or erased. 0 1 0 1 0 blocks 11 to 0 are protected. blocks 12 to 15 can be written or erased. 0 1 0 1 1 blocks 9 to 0 are protected. blocks 10 to 15 can be written or erased. 0 1 1 0 0 blocks 7 to 0 are protected. blocks 8 to 15 can be written or erased. 0 1 1 0 1 blocks 5 to 0 are protected. blocks 6 to 15 can be written or erased. 0 1 1 1 0 blocks 3 to 0 are protected. blocks 4 to 15 can be written or erased. 0 1 1 1 1 blocks 1 and 0 are protected. blocks 2 to 15 can be written or erased. 1 1 1 1 1 all blocks can be written or erased. other than above setting prohibited chapter 19 flash memory user?s manual u17446ej5v0ud 292 figure 19-17. format of protect byte (2/2) ? pd78f9234 prself4 prself3 prself2 prself1 prself0 status 0 0 0 0 0 blocks 31 to 0 are protected. 0 0 0 0 1 blocks 29 to 0 are protected. blocks 30 and 31 can be written or erased. 0 0 0 1 0 blocks 27 to 0 are protected. blocks 28 to 31 can be written or erased. 0 0 0 1 1 blocks 25 to 0 are protected. blocks 26 and 31 can be written or erased. 0 0 1 0 0 blocks 23 to 0 are protected. blocks 24 to 31 can be written or erased. 0 0 1 0 1 blocks 21 to 0 are protected. blocks 22 to 31 can be written or erased. 0 0 1 1 0 blocks 19 to 0 are protected. blocks 20 to 31 can be written or erased. 0 0 1 1 1 blocks 17 to 0 are protected. blocks 18 to 31 can be written or erased. 0 1 0 0 0 blocks 15 to 0 are protected. blocks 16 to 31 can be written or erased. 0 1 0 0 1 blocks 13 to 0 are protected. blocks 14 to 31 can be written or erased. 0 1 0 1 0 blocks 11 to 0 are protected. blocks 12 to 31 can be written or erased. 0 1 0 1 1 blocks 9 to 0 are protected. blocks 10 to 31 can be written or erased. 0 1 1 0 0 blocks 7 to 0 are protected. blocks 8 to 31 can be written or erased. 0 1 1 0 1 blocks 5 to 0 are protected. blocks 6 to 31 can be written or erased. 0 1 1 1 0 blocks 3 to 0 are protected. blocks 4 to 31 can be written or erased. 0 1 1 1 1 blocks 1 and 0 are protected. blocks 2 to 31 can be written or erased. 1 1 1 1 1 all blocks can be written or erased. other than above setting prohibited chapter 19 flash memory user?s manual u17446ej5v0ud 293 19.8.4 example of shifting norma l mode to self programming mode the operating mode must be shifted from normal mode to self programming mode before performing self programming. an example of shifting to self programming mode is explained below. <1> disable interrupts if the interrupt function is used (by setting the interrupt mask flag registers (mk0, mk1) to ffh and executing the di instruction). <2> clear flcmd (flcmd = 00h). <3> clear the flash status register (pfs). <4> set self programming mode using a specific sequence note . ? write a specific value (a5h) to pfcmd. ? write 01h to flpmc (writing in this step is invalid). ? write 0feh (inverted value of 01h) to flpmc (writing in this step is invalid). ? write 01h to flpmc (writing in this step is valid). <5> execute nop instructi on and halt instruction. <6> check the execution result of the specif ic sequence using bit 0 (fprerr) of pfs. abnormal <3>, normal <7> <7> mode shift is completed. note if the cpu clock is lower than 1 mhz, set it to be 1 mhz or higher. caution be sure to perform the series of operati ons described above using the user program at an address where data is not erased or written. chapter 19 flash memory user?s manual u17446ej5v0ud 294 figure 19-18. example of shifting to self programming mode shift to self programming mode <1> disable interrupts (by setting mk0 and mk1 to ffh and executing di instruction) pfcmd = a5h <6> check execution result (fprerr flag) abnormal normal ; when interrupt function is used if the cpu clock is lower than 1 mhz, set it to be 1 mhz or higher. <3> clear pfs <2> clear flcmd (flcmd = 00h) <7> termination flpmc = 01h (set value) flpmc = 0feh (inverted set value) flpmc = 01h (set value) nop instruction halt instruction ; set value is invalid ; set value is valid <4> <5> caution be sure to perform the series of operations described above using the user program at an address where data is not erased or written. remark <1> to <7> in figure 19-18 correspond to <1> to <7> in 19.8.4 (previous page). chapter 19 flash memory user?s manual u17446ej5v0ud 295 an example of the program that shifts the mode to self programming mode is shown below. ;---------------------------- ;start ;---------------------------- mov mk0,#11111111b ; masks all interrupts mov mk1,#11111111b mov flcmd,#00h ; clear flcmd register di modeonloop: ; configure settings so that the cpu clock 1 mhz mov pfs,#00h ; clears flash status register mov pfcmd,#0a5h ; pfcmd register control mov flpmc,#01h ; flpmc register control (sets value) mov flpmc,#0feh ; flpmc register control (inverts set value) mov flpmc,#01h ; sets self programming mode with flpmc register ; control (sets value) nop halt bt pfs.o,$modeonloop ; checks completion of write to specific registers ; repeats the same processing when an error occurs ;---------------------------- ;end ;---------------------------- chapter 19 flash memory user?s manual u17446ej5v0ud 296 19.8.5 example of shifting self programming mode to normal mode the operating mode must be returned from self programming mode to normal mode after performing self programming. an example of shifting to normal mode is explained below. <1> clear flcmd (flcmd = 00h). <2> clear the flash status register (pfs). <3> set normal mode using a specific sequence. ? write the specific value (a5h) to pfcmd. ? write 00h to flpmc (writing in this step is invalid) ? write 0ffh (inverted value of 00h) to flpmc (writing in this step is invalid) ? write 00h to flpmc (writing in this step is valid) <4> check the execution result of the spec ific sequence using bit 0 (fprerr) of pfs note . abnormal <2>, normal <5> <5> enable interrupt servicing (by executing the ei inst ruction and changing mk0 and mk1) to restore the original state. <6> mode shift is completed note restore the cpu clock to its setting before self pr ogramming, after normal execution of the specific sequence. caution be sure to perform the series of operations described above using the user program at an address where data is not erased or written. chapter 19 flash memory user?s manual u17446ej5v0ud 297 figure 19-19. example of sh ifting to normal mode shift to normal mode pfcmd = a5h <4> check execution result (fprerr flag) abnormal normal <1> clear flcmd (flcmd = 00h) <2> clear pfs <6> termination flpmc = 00h (set value) flpmc = 0ffh (inverted set value) flpmc = 00h (set value) ; set value is invalid ; set value is valid <5> enable interrupts (by executing ei instruction and changing mk0 and mk1) ; when interrupt function is used <3> restore the cpu clock to its setting before the self programming caution be sure to perform the series of operations described above using the user program at an address where data is not erased or written. remark <1> to <6> in figure 19-19 correspond to <1> to <6> in 19.8.5 (previous page). chapter 19 flash memory user?s manual u17446ej5v0ud 298 an example of a program that shifts the mode to normal mode is shown below. ;---------------------------- ;start ;---------------------------- mov flcmd,#00h ; clear flcmd register modeoffloop: mov pfs,#00h ; clears flash status register mov pfcmd,#0a5h ; pfcmd register control mov flpmc,#00h ; flpmc register control (sets value) mov flpmc,#0ffh ; flpmc register control (inverts set value) mov flpmc,#00h ; sets normal mode via flpmc register control (sets value) bt pfs.0,$modeoffloop ; checks completion of write to specific registers ; repeats the same processing when an error occurs ; restore the cpu clock to its setting before the self ; programming, after normal completion of the specific ; sequence mov mk0,#int_mk0 ; restores interrupt mask flag mov mk1,#int_mk1 ei ;---------------------------- ;end ;---------------------------- chapter 19 flash memory user?s manual u17446ej5v0ud 299 19.8.6 example of block erase operation in self programming mode an example of the block erase operation in self programming mode is explained below. <1> set 03h (block erase) to the flash program command register (flcmd). <2> set the block number to be erased, to flash address pointer h (flaph). <3> set flash address pointer l (flapl) to 00h. <4> write the same value as flaph to the flas h address pointer h compare register (flaphc). <5> set the flash address pointer l compare register (flaplc) to 00h. <6> clear the flash status register (pfs). <7> write ach to the watchdog timer enable register (wdte) (clear and restart the watchdog timer counter) note 1 . <8> execute the halt instruction then start self prog ramming. (execute an instruction immediately after the halt instruction if self programming has been executed.) <9> check if a self programming error has occurred using bit 1 (vcerr) and bit 2 (weprerr) of pfs note 2 . abnormal <10> normal <12> <10> if the number of times the erase command can be executed has not been exceeded, return to step <6> and re-execute the command. if the number of times t he erase command can be executed has been exceeded, block erasure ends abnormally. <11> block erase processing is abnormally terminated. <12> block erase processing is normally terminated. notes 1. this setting is not required when the watchdog timer is not used. 2. separately check the weprerr bit to check for errors in executing the erase command on a write- prohibited area. chapter 19 flash memory user?s manual u17446ej5v0ud 300 figure 19-20. example of block erase operation in self programming mode <7> clear & restart wdt counter (wdte = ach) note <9> check execution result <10> check the number of executions of the erase command <8> execute halt instruction <12> normal termination normal <6> clear pfs <1> set erase command (flcmd = 03h) <2> set no. of block to be erased to flaph block erasure <4> set the same value as that of flaph to flaphc <11> abnormal termination abnormal the erase command cannot be re-executed. <3> set flapl to 00h <5> set flaplc to 00h the erase command can be re-executed. note this setting is not required w hen the watchdog timer is not used. remark <1> to <12> in figure 19-20 correspond to <1> to <12> in 19.8.6 (previous page). chapter 19 flash memory user?s manual u17446ej5v0ud 301 an example of a program that performs a block erase in self programming mode is shown below. ;---------------------------- ;start ;---------------------------- mov b,#48 ; specifies the number of times the erase command can be ; executed. ; (4.0 v to 5.5 v time for executing block erasure 100 times) flashblockerase: mov flcmd,#03h ; sets flash control command (block erase) mov flaph,#07h ; sets number of block to be erased (block 7 is specified here) mov flapl,#00h ; fixes flapl to ?00h? mov flaphc,#07h ; sets erase block compare number (same value as that of flaph) mov flaplc,#00h ; fixes flaplc to ?00h? eraseretry: mov pfs,#00h ; clears flash status register mov wdte,#0ach ; clears & restarts wdt halt ; self programming is started mov a,pfs cmp a,#00h ; checks execution result bz $statusnormal ; normal termination dbnz b,$eraseretry ; checks whether to re-execute the erase command. ;--------------------------------------------------------------------- ;end (abnormal termination processing); perform processing to shift to normal mode in order to return to normal processing ;--------------------------------------------------------------------- statuserror: ;--------------------------------------------------------------------- ;end (normal termination processing) ;--------------------------------------------------------------------- statusnormal: chapter 19 flash memory user?s manual u17446ej5v0ud 302 19.8.7 example of block blank chec k operation in self programming mode an example of the block blank check operation in self programming mode is explained below. <1> set 04h (block blank check) to the flash program command register (flcmd). <2> set the number of block for which a blank check is performed, to flash address pointer h (flaph). <3> set flash address pointer l (flapl) to 00h. <4> write the same value as flaph to the flas h address pointer h compare register (flaphc). <5> set the flash address pointer l compare register (flaplc) to ffh. <6> clear the flash status register (pfs). <7> write ach to the watchdog timer enable register (wdte) (clear and restart the watchdog timer counter) note . <8> execute the halt instruction then start self prog ramming. (execute an instruction immediately after the halt instruction if self programming has been executed.) <9> check if a self programming error has occurred using bit 1 (vcerr) and bit 2 (weprerr) of pfs. abnormal <10> normal <11> <10> block blank check is abnormally terminated. <11> block blank check is normally terminated. note this setting is not required w hen the watchdog timer is not used. chapter 19 flash memory user?s manual u17446ej5v0ud 303 figure 19-21. example of block blank ch eck operation in self programming mode <11> normal termination <7> clear & restart wdt counter (wdte = ach) note <9> check execution result (vcerr and weprerr flags) <8> execute halt instruction normal abnormal <6> clear pfs <1> set block blank check command (flcmd = 04h) <2> set no. of block for blank check to flaph block blank check <10> abnormal termination <5> set flaplc to 00h <4> set the same value as that of flaph to flaphc <3> set flapl to 00h note this setting is not required w hen the watchdog timer is not used. remark <1> to <11>in figure 19-21 correspond to <1> to <11> in 19.8.7 (previous page). chapter 19 flash memory user?s manual u17446ej5v0ud 304 an example of a program that performs a block blank check in self programming mode is shown below. ;---------------------------- ;start ;---------------------------- flashblockblankcheck: mov flcmd,#04h ; sets flash control command (block blank check) mov flaph,#07h ; sets number of block for blank check (block 7 is specified ; here) mov flapl,#00h ; fixes flapl to ?00h? mov flaphc,#07h ; sets blank check block compare number (same value as that of ; flaph) mov flaplc,#0ffh ; fixes flaplc to ?ffh? mov pfs,#00h ; clears flash status register mov wdte,#0ach ; clears & restarts wdt halt ; self programming is started mov a,pfs mov cmdstatus,a ; execution result is stored in variable ; (cmdstatus = 0: normal termination, other than 0: abnormal ; termination) ;---------------------------- ;end ;---------------------------- chapter 19 flash memory user?s manual u17446ej5v0ud 305 19.8.8 example of byte write operation in self programming mode an example of the byte write operation in self programming mode is explained below. <1> set 05h (byte write) to the flash program command register (flcmd). <2> set the number of block to which data is to be written, to flash address pointer h (flaph). <3> set the address at which data is to be wr itten, to flash address pointer l (flapl). <4> set the data to be written, to t he flash write buffer register (flw). <5> clear the flash status register (pfs). <6> write ach to the watchdog timer enable register (wdte) (clear and restart the watchdog timer counter) note . <7> execute the halt instruction t hen start self programming. (execute an instruction immediately after the halt instruction if self programming has been executed.) <8> check if a self programming error has occurred using bit 1 (vcerr) and bit 2 (weprerr) of pfs. abnormal <9> normal <10> <9> byte write processing is abnormally terminated. <10> byte write processing is normally terminated. note this setting is not required when the watchdog timer is not used. caution if a write results in failure, er ase the block once and write to it again. chapter 19 flash memory user?s manual u17446ej5v0ud 306 figure 19-22. example of byte write operation in self programming mode <10> normal termination <6> clear & restart wdt counter (wdte = ach) note <8> check execution result (vcerr and weprerr flags) <7> execute halt instruction normal abnormal <5> clear pfs <1> set byte write command (flcmd = 05h) byte write <9> abnormal termination <4> set data to be written to flw <2> set no. of block to be written, to flaph <3> set address at which data is to be written, to flapl note this setting is not required w hen the watchdog timer is not used. remark <1> to <10> in figure 19-22 correspond to <1> to <10> in 19.8.8 (previous page). chapter 19 flash memory user?s manual u17446ej5v0ud 307 an example of a program that performs a byte write in self programming mode is shown below. ;---------------------------- ;start ;---------------------------- flashwrite: mov flcmd,#05h ; sets flash control command (byte write) mov flaph,#07h ; sets address to which data is to be written, with ; flaph (block 7 is specified here) mov flapl,#20h ; sets address to which data is to be written, with ; flapl (address 20h is specified here) mov flw,#10h ; sets data to be written (10h is specified here) mov pfs,#00h ; clears flash status register mov wdte,#0ach ; clears & restarts wdt halt ; self programming is started mov a,pfs mov cmdstatus,a ; execution result is stored in variable ; (cmdstatus = 0: normal termination, other than 0: abnormal ; termination) ;---------------------------- ;end ;---------------------------- chapter 19 flash memory user?s manual u17446ej5v0ud 308 19.8.9 examples of internal verif y operation in self programming mode examples of internal verify 1 and 2 operatio ns in self programming mode are explained below. ? internal verify 1 <1> set 01h (internal verify 1) to the flash program command register (flcmd). <2> set the block number for which internal verify is performed, to flash address pointer h (flaph). <3> set 00h to the flash address pointer l (flapl). <4> write the same value as that of flaph to t he flash address pointer h compare register (flaphc). <5> set ffh to the flash address pointer l compare register (flaplc). <6> clear the flash status register (pfs). <7> write ach to the watchdog timer enable register (wdte) (clear and restart the watchdog timer counter) note . <8> execute the halt instruction then start self progra mming. (execute an instruction immediately after the halt instruction if self programming has been executed.) <9> check if a self programming error has occurred using bit 1 (vcerr) and bit 2 (weprerr) of pfs. abnormal <10> normal <11> <10> internal verify processing is terminated abnormally. <11> internal verify processing is terminated normally. ? internal verify 2 <1> set 02h (internal verify 2) to the flash program command register (flcmd). <2> set the block number for which internal verify is performed, to flash address pointer h (flaph). <3> set the verify start address to the flash address pointer l (flapl). <4> write the same value as that of flaph to t he flash address pointer h compare register (flaphc). <5> set the verify end address to the flash address pointer l compare register (flaplc). <6> clear the flash status register (pfs). <7> write ach to the watchdog timer enable register (wdte) (clear and restart the watchdog timer counter) note . <8> execute the halt instruction then start self prog ramming. (execute an instruction immediately after the halt instruction if self programming has been executed.) <9> check if a self programming error has occurred using bit 1 (vcerr) and bit 2 (weprerr) of pfs. abnormal <10> normal <11> <10> internal verify processing is terminated abnormally. <11> internal verify processing is terminated normally. note this setting is not required when the watchdog timer is not used. chapter 19 flash memory user?s manual u17446ej5v0ud 309 figure 19-23. example of internal verify 1 operation in self programming mode <11> normal termination <7> clear & restart wdt counter (wdte = ach) note <9> check execution result (vcerr and weprerr flags) <8> execute halt instruction normal abnormal <6> clear pfs <1> set internal verify 1 command (flcmd = 01h) internal verify 1 <10> abnormal termination <2> set block no. for internal verify, to flaph <4> set the same value as that of flaph to flaphc <5> set ffh to flaplc <3> set 00h to flapl note this setting is not required when the watchdog timer is not used. remark <1> to <11> in figure 19-23 correspond to <1> to <11> of internal verify 1 in 19.8.9 (previous page). chapter 19 flash memory user?s manual u17446ej5v0ud 310 figure 19-24. example of internal verify 2 operation in self programming mode <11> normal termination <7> clear & restart wdt counter (wdte = ach) note <9> check execution result (vcerr and weprerr flags) <8> execute halt instruction normal abnormal <6> clear pfs <1> set internal verify 2 command (flcmd = 02h) internal verify 2 <10> abnormal termination <2> set block no. for internal verify, to flaph <4> set the same value as that of flaph to flaphc <5> sets flaplc to the end address <3> sets flapl to the start address note this setting is not required when the watchdog timer is not used. remark <1> to <11> in figure 19-24 correspond to <1> to <11> of internal verify 2 in 19.8.9 (the page before last). chapter 19 flash memory user?s manual u17446ej5v0ud 311 example programs that perform internal verify 1 and 2 in self programming mode are shown below. ? internal verify 1 ;---------------------------- ;start ;---------------------------- flashverify: mov flcmd,#01h ; sets flash control command (internal verify 1) mov flaph,#07h ; sets block number for which internal verify is performed, ; to flaph (example: block 7 is specified here) mov flapl,#00h ; sets 00h mov flaphc,#07h mov flaplc,#ffh ; sets ffh mov pfs,#00h ; clears flash status register mov wdte,#0ach ; clears & restarts wdt halt ; self programming is started mov a,pfs mov cmdstatus,a ; execution result is stored in variable ; (cmdstatus = 0: normal termination, other than 0: abnormal ; termination) ;---------------------------- ;end ;---------------------------- ? internal verify 2 ;---------------------------- ;start ;---------------------------- flashverify: mov flcmd,#02h ; sets flash control command (internal verify 2) mov flaph,#07h ; sets block number for which internal verify is ; performed, to flaph (example: block 7 is specified here) mov flapl,#00h ; sets flapl to the start address for verify (example: address ; 00h is specified here) mov flaphc,#07h mov flaplc,#20h ; sets flaplc to the end address for verify (example: address ; 20h is specified here) mov pfs,#00h ; clears flash status register mov wdte,#0ach ; clears & restarts wdt halt ; self programming is started mov a,pfs mov cmdstatus,a ; execution result is stored in variable ; (cmdstatus = 0: normal termination, other than 0: abnormal ; termination) ;---------------------------- ;end ;---------------------------- chapter 19 flash memory user?s manual u17446ej5v0ud 312 19.8.10 examples of operation wh en command execution time should be minimized in self programming mode examples of operation when the comm and execution time should be minimized in self programming mode are explained below. (1) erasure to blank check <1> mode is shifted from normal mode to self programming mode (<1> to <7> in 19.8.4 ) <2> execution of block erase error check (<1> to <12> in 19.8.6 ) <3> execution of block blank check error check (<1> to <11> in 19.8.7 ) <4> mode is shifted from self programming mode to normal mode (<1> to <6> in 19.8.5 ) figure 19-25. example of operation when command execution time should be minimized (from erasure to blank check) <4> shift to normal mode abnormal <1> shift to self programming mode erasure to blank check abnormal termination note <2> execute block erase <3> execute block blank check <2> check execution result (vcerr and weprerr flags) <3> check execution result (vcerr and weprerr flags) normal termination normal abnormal normal figure 19-20 <1> to <12> figure 19-21 <1> to <11> figure 19-18 <1> to <7> figure 19-19 <1> to <6> note perform processing to shift to normal mode in order to return to normal processing. remark <1> to <4> in figure 19-25 correspond to <1> to <4> in 19.8.10 (1) above. chapter 19 flash memory user?s manual u17446ej5v0ud 313 an example of a program when the command execution time (from erasure to black check) should be minimized in self programming mode is shown below. ;--------------------------------------------------------------------- ;start ;--------------------------------------------------------------------- mov mk0,#11111111b ; masks all interrupts mov mk1,#11111111b mov flcmd,#00h ; clears flcmd register di modeonloop: ; configure settings so that the cpu clock 1 mhz mov pfs,#00h ; clears flash status register mov pfcmd,#0a5h ; pfcmd register control mov flpmc,#01h ; flpmc register control (sets value) mov flpmc,#0feh ; flpmc register control (inverts set value) mov flpmc,#01h ; sets self programming mode with flpmc register control (sets ; value) nop halt bt pfs.0,$modeonloop ; checks completion of write to specific registers ; repeats the same processing when an error occurs flashblockerase: mov flcmd,#03h ; sets flash control command (block erase) mov flaph,#07h ; sets number of block to be erased (block 7 is specified ; here) mov flapl,#00h ; fixes flapl to ?00h? mov flaphc,#07h ; sets erase block compare number (same value as that of ; flaph) mov flaplc,#00h ; fixes flaplc to ?00h? mov wdte,#0ach ; clears & restarts wdt halt ; self programming is started mov a,pfs cmp a,#00h bnz $statuserror ; checks erase error ; performs abnormal termination processing when an error ; occurs flashblockblankcheck: mov flcmd,#04h ; sets flash control command (block blank check) mov flaph,#07h ; sets number of block for blank check (block 7 is specified ; here) mov flapl,#00h ; fixes flapl to ?00h? chapter 19 flash memory user?s manual u17446ej5v0ud 314 mov flaphc,#07h ; sets blank check block compare number (same value as of ; flaph) mov flaplc,#0ffh ; fixes flaplc to ?ffh? mov wdte,#0ach ; clears & restarts wdt halt ; self programming is started mov a,pfs cmp a,#00h bnz $statuserror ; checks blank check error ; performs abnormal termination processing when an error ; occurs mov flcmd,#00h ; clears flcmd register modeoffloop: mov pfs,#00h ; clears flash status register mov pfcmd,#0a5h ; pfcmd register control mov flpmc,#00h ; flpmc register control (sets value) mov flpmc,#0ffh ; flpmc register control (inverts set value) mov flpmc,#00h ; sets normal mode via flpmc register control (sets value) bt pfs.0,$modeoffloop ; checks completion of write to specific registers ; repeats the same processing when an error occurs ; restore the cpu clock to its setting before the self ; programming, after normal completion of the specific ; sequence mov mk0,#int_mk0 ; restores interrupt mask flag mov mk1,#int_mk1 ei br statusnormal ;--------------------------------------------------------------------- ;end (abnormal termination processing); perform processing to shift to normal mode in order to return to normal processing ;--------------------------------------------------------------------- statuserror: ;--------------------------------------------------------------------- ;end (normal termination processing) ;--------------------------------------------------------------------- statusnormal: chapter 19 flash memory user?s manual u17446ej5v0ud 315 (2) write to internal verify <1> mode is shifted from normal mode to self programming mode (<1> to <7> in 19.8.4 ) <2> specification of source data for write <3> execution of byte write error check (<1> to <10> in 19.8.8 ) <4> <3> is repeated unt il all data are written. <5> execution of internal verify 2 error check (<1> to <11> in 19.8.9 ) <6> mode is shifted from self programming mode to normal mode (<1> to <6> in 19.8.5 ) figure 19-26. example of operation when command execution time should be minimized (from write to internal verify) <6> shift to normal mode abnormal <1> shift to self programming mode write to internal verify <3> execute byte write command <5> execute internal verify 2 command <3> check execution result (vcerr and weprerr flags) <5> check execution result (vcerr and weprerr flags) normal termination normal abnormal normal figure 19-22 <1> to <10> figure 19-23 <1> to <11> figure 19-19 <1> to <6> <2> set source data for write <4> all data written? yes no figure 19-18 <1> to <7> abnormal termination note note perform processing to shift to normal mo de in order to return to normal processing. remark <1> to <6> in figure 19-26 correspond to <1> to <6> in 19.8.10 (2) above. chapter 19 flash memory user?s manual u17446ej5v0ud 316 an example of a program when the comm and execution time (from write to internal verify) should be minimized in self programming mode is shown below. ;--------------------------------------------------------------------- ;start ;--------------------------------------------------------------------- mov mk0,#11111111b ; masks all interrupts mov mk1,#11111111b mov flcmd,#00h ; clears flcmd register di modeonloop: ; configure settings so that the cpu clock 1 mhz mov pfs,#00h ; clears flash status register mov pfcmd,#0a5h ; pfcmd register control mov flpmc,#01h ; flpmc register control (sets value) mov flpmc,#0feh ; flpmc register control (inverts set value) mov flpmc,#01h ; sets self programming mode with flpmc register control ; (sets value) nop halt bt pfs.0,$modeonloop ; checks completion of write to specific registers ; repeats the same processing when an error occurs flashwrite: movw hl,#dataadrtop ; sets address at which data to be written is located movw de,#writeadr ; sets address at which data is to be written flashwriteloop: mov flcmd,#05h ; sets flash control command (byte write) mov a,d mov flaph,a ; sets address at which data is to be written mov a,e mov flapl,a ; sets address at which data is to be written mov a,[hl] mov flw,a ; sets data to be written mov wdte,#0ach ; clears & restarts wdt halt ; self programming is started mov a,pfs cmp a,#00h bnz $statuserror ; checks write error ; performs abnormal termination processing when an error ; occurs incw hl ; address at which data to be written is located + 1 movw ax,hl cmpw ax,#dataadrbtm ; performs internal verify processing bnc $flashverify ; if write of all data is completed chapter 19 flash memory user?s manual u17446ej5v0ud 317 incw de ; address at which data is to be written + 1 br flashwriteloop flashverify: movw hl,#writeadr ; sets verify address mov flcmd,#02h ; sets flash control command (internal verify 2) mov a,h mov flaph,a ; sets verify start address mov a,l mov flapl,a ; sets verify start address mov a,d mov flaphc,a ; sets verify end address mov a,e mov flaplc,a ; sets verify end address mov wdte,#0ach ; clears & restarts wdt halt ; self programming is started mov a,pfs cmp a,#00h bnz $statuserror ; checks internal verify error ; performs abnormal termination processing when an error ; occurs mov flcmd,#00h ; clears flcmd register modeoffloop: mov pfs,#00h ; clears flash status register mov pfcmd,#0a5h ; pfcmd register control mov flpmc,#00h ; flpmc register control (sets value) mov flpmc,#0ffh ; flpmc register control (inverts set value) mov flpmc,#00h ; sets normal mode via flpmc register control (sets value) bt pfs.0,$modeoffloop ; checks completion of write to specific registers ; repeats the same processing when an error occurs ; restore the cpu clock to its setting before the self ; programming, after normal completion of the specific ; sequence mov mk0,#int_mk0 ; restores interrupt mask flag mov mk1,#int_mk1 ei br statusnormal ;--------------------------------------------------------------------- ;end (abnormal termination processing); perform processing to shift to normal mode in order to return to normal processing chapter 19 flash memory user?s manual u17446ej5v0ud 318 ;--------------------------------------------------------------------- statuserror: ;--------------------------------------------------------------------- ;end (normal termination processing) ;--------------------------------------------------------------------- statusnormal: ;--------------------------------------------------------------------- ; data to be written ;--------------------------------------------------------------------- dataadrtop: db xxh db xxh db xxh db xxh : : db xxh dataadrbtm: ;--------------------------------------------------------------------- remark internal verify 2 is used in the above program example. use internal verify 1 to verify a whole block. chapter 19 flash memory user?s manual u17446ej5v0ud 319 19.8.11 examples of operation when interrupt-disabled time should be minimized in self programming mode examples of operation when the interrupt-disabled ti me should be minimized in self programming mode are explained below. (1) erasure to blank check <1> specification of block erase command (<1> to <5> in 19.8.6 ) <2> mode is shifted from normal mode to self programming mode (<1> to <7> in 19.8.4 ) <3> execution of block erase command error check (<6> to <12> in 19.8.6 ) <4> mode is shifted from self programming mode to normal mode (<1> to <6> in 19.8.5 ) <5> specification of block blank check command (<1> to <5> in 19.8.7 ) <6> mode is shifted from normal mode to self programming mode (<1> to <7> in 19.8.4 ) <7> execution of block blank check command error check (<6> to <11> in 19.8.7 ) <8> mode is shifted from self programming mode to normal mode (<1> to <6> in 19.8.5 ) chapter 19 flash memory user?s manual u17446ej5v0ud 320 figure 19-27. example of operation when in terrupt-disabled time should be minimized (from erasure to blank check) abnormal erasure to blank check abnormal termination note <1> specify block erase command <3> check execution result normal termination normal abnormal figure 19-20 <1> to <5> <2> shift to self programming mode figure 19-18 <1> to <7> <3> execute block erase command figure 19-20 <6> to <12> <4> shift to normal mode figure 19-19 <1> to <6> <5> specify block blank check command <7> check execution result (vcerr and weprerr flags) figure 19-21 <1> to <5> <6> shift to self programming mode figure 19-18 <1> to <7> <7> execute block blank check command figure 19-21 <6> to <11> <8> shift to normal mode figure 19-19 <1> to <6> normal note perform processing to shift to normal mo de in order to return to normal processing. remark <1> to <8> in figure 19-27 correspond to <1> to <8> in 19.8.11 (1) (previous page). chapter 19 flash memory user?s manual u17446ej5v0ud 321 an example of a program when the interrupt-disabled time (from erasure to blank check) should be minimized in self programming mode is shown below. ;--------------------------------------------------------------------- ;start ;--------------------------------------------------------------------- mov b,#48 ; specifies the number of times the erase command can be ; executed. ; (4.0 v to 5.5 v time for executing block erasure 100 times) flashblockerase: ; sets erase command mov flcmd,#03h ; sets flash control command (block erase) mov flaph,#07h ; sets number of block to be erased (block 7 is specified here) mov flapl,#00h ; fixes flapl to ?00h? mov flaphc,#07h ; sets erase block compare number (same value as that of flaph) mov flaplc,#00h ; fixes flaplc to ?00h? call !modeon ; shift to self programming mode eraseretry: ; execution of erase command mov pfs,#00h ; clears flash status register mov wdte,#0ach ; clears & restarts wdt halt ; self programming is started mov a,pfs cmp a,#00h ; checks execution result bnz $retrycheck ; checks erase error ; performs abnormal termination processing when an error ; occurs. call !modeoff ; shift to normal mode ; sets blank check command mov flcmd,#04h ; sets flash control command (block blank check) mov flaph,#07h ; sets block number for blank check (block 7 is specified here) mov flapl,#00h ; fixes flapl to ?00h? mov flaphc,#07h ; sets blank check block compare number (same value as that of ; flaph) mov flaplc,#0ffh ; fixes flaplc to ?ffh? call !modeon ; shift to self programming mode ; execution of blank check command mov pfs,#00h ; clears flash status register mov wdte,#0ach ; clears & restarts wdt halt ; self programming is started mov a,pfs chapter 19 flash memory user?s manual u17446ej5v0ud 322 cmp a,#00h ; checks execution result bnz $statuserror ; checks blank check error ; performs abnormal termination processing when an error occurs call !modeoff ; shift to normal mode br statusnormal retrycheck: dbnz b,$eraseretry ;--------------------------------------------------------------------- ;end (abnormal termination processing); perform processing to shift to normal mode in order to return to normal processing ;--------------------------------------------------------------------- statuserror: ;--------------------------------------------------------------------- ;end (normal termination processing) ;--------------------------------------------------------------------- statusnormal: ;--------------------------------------------------------------------- ;processing to shift to self programming mode ;--------------------------------------------------------------------- modeon: mov mk0,#11111111b ; masks all interrupts mov mk1,#11111111b mov flcmd,#00h ; clears flcmd register di modeonloop: ; configure settings so that the cpu clock 1 mhz mov pfs,#00h ; clears flash status register mov pfcmd,#0a5h ; pfcmd register control mov flpmc,#01h ; flpmc register control (sets value) mov flpmc,#0feh ; flpmc register control (inverts set value) mov flpmc,#01h ; sets self programming mode via flpmc register control (sets ; value) nop halt bt pfs.0,$modeonloop ; checks completion of write to specific registers ; repeats the same processing when an error occurs ret chapter 19 flash memory user?s manual u17446ej5v0ud 323 ;--------------------------------------------------------------------- ; processing to shift to normal mode ;--------------------------------------------------------------------- modeoffloop: mov flcmd,#00h ; clears flcmd register mov pfs,#00h ; clears flash status register mov pfcmd,#0a5h ; pfcmd register control mov flpmc,#00h ; flpmc register control (sets value) mov flpmc,#0ffh ; flpmc register control (inverts set value) mov flpmc,#00h ; sets normal mode via flpmc register control (sets value) bt pfs.0,$modeoffloop ; checks completion of write to specific registers ; repeats the same processing when an error occurs ; restore the cpu clock to its setting before the self ; programming, after normal completion of the specific ; sequence mov mk0,#int_mk0 ; restores interrupt mask flag mov mk1,#int_mk1 ei ret chapter 19 flash memory user?s manual u17446ej5v0ud 324 (2) write to internal verify <1> specification of source data for write <2> specification of byte write command (<1> to <4> in 19.8.8 ) <3> mode is shifted from normal mode to self programming mode (<1> to <7> in 19.8.4 ) <4> execution of byte write command error check (<5> to <10> in 19.8.8 ) <5> mode is shifted from self programming mode to normal mode (<1> to <6> in 19.8.5 ) <6> <2> to <5> is repeated until all data are written. <7> the internal verify command is specified (<1> to <5> in 19.8.9 ) <8> mode is shifted from normal mode to self programming mode (<1> to <7> in 19.8.4 ) <9> execution of internal verify command error check (<6> to <11> in 19.8.9 ) <10> mode is shifted from self programming mode to normal mode (<1> to <6> in 19.8.5 ) chapter 19 flash memory user?s manual u17446ej5v0ud 325 figure 19-28. example of operation when in terrupt-disabled time should be minimized (from write to internal verify) abnormal abnormal termination note <2> specify byte write command <4> check execution result (vcerr and weprerr flags) normal termination normal abnormal figure 19-22 <1> to <4> <3> shift to self programming mode figure 19-18 <1> to <7> <4> execute byte write command figure 19-22 <5> to <10> <5> shift to normal mode figure 19-19 <1> to <6> <7> specify internal verify command <9> check execution result (vcerr and weprerr flags) figure 19-23 <1> to <5> <8> shift to self programming mode figure 19-18 <1> to <7> <9> execute internal verify command figure 19-23 <6> to <11> <10> shift to normal mode figure 19-19 <1> to <6> normal <1> set source data for write write to internal verify <6> all data written? yes no note perform processing to shift to normal mo de in order to return to normal processing. remark <1> to <10> in figure 19-28 correspond to <1> to <10> in 19.8.11 (2) (previous page). chapter 19 flash memory user?s manual u17446ej5v0ud 326 an example of a program when the interrupt-disabled time (f rom write to internal verify) should be minimized in self programming mode is shown below. ;--------------------------------------------------------------------- ;start ;--------------------------------------------------------------------- ; sets write command flashwrite: movw hl,#dataadrtop ; sets address at which data to be written is located movw de,#writeadr ; sets address at which data is to be written flashwriteloop: mov flcmd,#05h ; sets flash control command (byte write) mov a,d mov flaph,a ; sets address at which data is to be written mov a,e mov flapl,a ; sets address at which data is to be written mov a,[hl] mov flw,a ; sets data to be written call !modeon ; shift to self programming mode ; execution of write command mov pfs,#00h ; clears flash status register mov wdte,#0ach ; clears & restarts wdt halt ; self programming is started mov a,pfs cmp a,#00h bnz $statuserror ; checks write error ; performs abnormal termination processing when an error ; occurs call !modeoff ; shift to normal mode mov mk0,#int_mk0 ; restores interrupt mask flag mov mk1,#int_mk1 ei ; judgment of writing all data incw hl ; address at which data to be written is located + 1 movw ax,hl cmpw ax,#dataadrbtm ; performs internal verify processing bnc $flashverify ; if write of all data is completed incw de ; address at which data is to be written + 1 br flashwriteloop chapter 19 flash memory user?s manual u17446ej5v0ud 327 ; setting internal verify command flashverify: movw hl,#writeadr ; sets verify address mov flcmd,#02h ; sets flash control command (internal verify 2) mov a,h mov flaph,a ; sets verify start address mov a,l mov flapl,a ; sets verify start address mov a,d mov flaphc,a ; sets verify end address mov a,e mov flaplc,a ; sets verify end address call !modeon ; shift to self programming mode ; execution of internal verify command mov pfs,#00h ; clears flash status register mov wdte,#0ach ; clears & restarts wdt halt ; self programming is started mov a,pfs cmp a,#00h bnz $statuserror ; checks internal verify error ; performs abnormal termination processing when an error occurs call !modeoff ; shift to normal mode br statusnormal ;--------------------------------------------------------------------- ;end (abnormal termination processing); perform processing to shift to normal mode in order to return to normal processing ;--------------------------------------------------------------------- statuserror: ;--------------------------------------------------------------------- ;end (normal termination processing) ;--------------------------------------------------------------------- statusnormal: chapter 19 flash memory user?s manual u17446ej5v0ud 328 ;--------------------------------------------------------------------- ;processing to shift to self programming mode ;--------------------------------------------------------------------- modeon: mov mk0,#11111111b ; masks all interrupts mov mk1,#11111111b mov flcmd,#00h ; clears flcmd register di modeonloop: ; configure settings so that the cpu clock 1 mhz mov pfs,#00h ; clears flash status register mov pfcmd,#0a5h ; pfcmd register control mov flpmc,#01h ; flpmc register control (sets value) mov flpmc,#0feh ; flpmc register control (inverts set value) mov flpmc,#01h ; sets self programming mode via flpmc register control (sets ; value) nop halt bt pfs.0,$modeonloop ; checks completion of write to specific registers ; repeats the same processing when an error occurs ret ;--------------------------------------------------------------------- ; processing to shift to normal mode ;--------------------------------------------------------------------- modeoffloop: mov flcmd,#00h ; clears flcmd register mov pfs,#00h ; clears flash status register mov pfcmd,#0a5h ; pfcmd register control mov flpmc,#00h ; flpmc register control (sets value) mov flpmc,#0ffh ; flpmc register control (inverts set value) mov flpmc,#00h ; sets normal mode via flpmc register control (sets value) bt pfs.0,$modeoffloop ; checks completion of write to specific registers ; repeats the same processing when an error occurs ; restore the cpu clock to its setting before the self ; programming, after normal completion of the specific ; sequence mov mk0,#int_mk0 ; restores interrupt mask flag mov mk1,#int_mk1 ei ret chapter 19 flash memory user?s manual u17446ej5v0ud 329 ;--------------------------------------------------------------------- ;data to be written ;--------------------------------------------------------------------- dataadrtop: db xxh db xxh db xxh db xxh : : db xxh dataadrbtm: ;--------------------------------------------------------------------- remark internal verify 2 is used in the above program example. use internal verify 1 to verify a whole block. user?s manual u17446ej5v0ud 330 chapter 20 on-chip debug function 20.1 connecting qb-mini2 to 78k0s/kb1+ the 78k0s/kb1+ uses reset, x1, x2, intp3, v dd , and gnd pins to communicate with the host machine via an on-chip debug emulator (qb-mini2). caution the 78k0s/kb1+ has an on-chip debug f unction, which is provided for development and evaluation. do not use the on-chip debug func tion in products designa ted for mass production, because the guaranteed nu mber of rewritable times of the flash memory may be exceeded when this function is used, and product reliability th erefore cannot be guaranteed. nec electronics is not liable for problems occurring when the on-chip debug function is used. figure 20-1. recommended circuit connection target connector target device reset circuit gnd reset note 1 x2 note 2 x1 note 2 intp3 note 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 reset_out reset signal data gnd data r.f.u. r.f.u. h/s note 4 note 3 note 3 clk r.f.u. r.f.u. intp r.f.u. clk reset_in r.f.u. 1 k 1 k 10 k v dd v dd 3 to 10 k v dd v dd v dd v dd 1 to 10 k v dd caution the constants described in the circuit connection example are reference values. if you perform flash programming aiming at mass pr oduction, thoroughly evaluate whether the specifications of the targ et device are satisfied. notes 1. the reset pin is used to download the monitor program at debugger startup or to implement forced reset. therefore, a pin that alternately functions as the reset pi n cannot be used. for reset pin connection, refer to qb-mini2 user?s manual (u18371e) . 2. this is the pin connection when the x1 and x2 pi ns are not used in the target system. when using the x1 and x2 pins, refer to 20.1.2 connection of x1 and x2 pins . 3. no problem will occur if the dashed line portions are connected. chapter 20 on-chip debug function user?s manual u17446ej5v0ud 331 notes 4. this pin is connected to enhance the accuracy of time measurement between run and break during debugging. debugging is possible even if this pin is left open, but measurement error occurs in several ms units. 5. the intp3 pin is used for communication between qb-mini2 and the target device during debugging. when debugging is performed with qb -mini2, therefore, the intp3 pin and its alternate-function pin cannot be used. for intp3 pin connection, refer to 20.1.1 connection of intp3 pin . pins for communication depend on whether the monitor program has been written or not. (refer to table 20-1 ) x1 and x2 pins can be used as i/o port pins or the pins fo r oscillation, after the moni tor program has been written. table 20-1. pins for communication with qb-mini2 before writing the monitor program after writing the monitor program x1, x2, reset, intp3, v dd , v ss reset, intp3, v dd , v ss 20.1.1 connection of intp3 pin the intp3 pin is used only for communication betwe en qb-mini2 and the target device during debugging. design circuits appropriately according to th e relevant case among the cases shown below. (1) intp3 pin is not used in tar get system (as is illustrated in figure 20-1 . recommended circuit connection ) see figure 20-2 . (2) qb-mini2 is used only for programming, not for debugging see figure 20-3 . (3) qb-mini2 is used for debugging and debugging of the intp3 pin is performed only with a real machine see figure 20-4 . figure 20-2. circuit connection for the case wher e intp3 pin is not used in target system intp3 target connector target device intp 1 k 12 v dd figure 20-3. circuit connection for the case where qb-mini2 is used only for programming intp3 target connector target device intp 12 chapter 20 on-chip debug function user?s manual u17446ej5v0ud 332 figure 20-4. circuit connection for the c ase where qb-mini2 is us ed for debugging and debugging of intp3 pin is performed only with real machine intp3 target connector target device intp 1 k 12 2 3 1 i/o to intp3 external device v dd * jumper setting when debugging with qb-mini2 connected: 1-2 shorted other than above: 2-3 shorted caution if debugging is performed with a real mach ine running, without using qb-mini2, write the user program using the qb-programmer. programs downloaded by the debugger include the monitor program, and such a program malfunctions if it is not controlled via qb-mini2. 20.1.2 connection of x1 and x2 pins the x1 and x2 pins are used when t he debugger is started for the first time (when downloading the monitor program) and when programming is perf ormed with the qb-programmer. figure 20-5. circuit connection for the case where x1 and x2 pins are used in target system x2 target connector target device x2 3 2 3 1 x1 2 3 1 x1 external components oscillator or external device 9 * jumper setting when debugger is started for the first time (downloading the monitor program) or when programming is performed with qb-programmer: 1-2 shorted other than above: 2-3 shorted chapter 20 on-chip debug function user?s manual u17446ej5v0ud 333 20.2 securing of user resources the user must prepare the following to perform communication between qb-mini2 and the target device and implement each debug function. for details of the setting, refer to qb-mini2 user?s manual (u18371e). ? securement of memory space the shaded portions in figure 20-6 are the areas re served for placing the debug monitor program, so user programs cannot be allocated in these spaces. figure 20-6. memory spaces where de bug monitor programs are allocated intp3 interrupt vector (2 bytes) for software break (2 bytes) 0x7eh internal rom end address 304 bytes internal rom space internal ram space stack area for debugging (5 bytes) 0x18h internal ram end address ? securement of serial interface for communication the register settings, concerning the intp3 pin us ed for communication between qb-mini2 and the target device, performed by the debug moni tor program must not be changed. user?s manual u17446ej5v0ud 334 chapter 21 instruction set overview this chapter lists the instruction set of the 78k0s/kb1+. for details of the operation and machine language (instruction code) of each instruction, refer to 78k/0s series instructions user?s manual (u11047e) . 21.1 operation 21.1.1 operand identifier s and description methods operands are described in ?operand? column of each inst ruction in accordance with th e description method of the instruction operand identifier (refer to the assembler spec ifications for details). when there are two or more description methods, select one of them. uppercase lette rs and the symbols #, !, $, and [ ] are key words and are described as they are. each symbol has the following meaning. ? #: immediate data specification ? !: absolute address specification ? $: relative address specification ? [ ]: indirect address specification in the case of immediate data, describe an appropriate nu meric value or a label. when using a label, be sure to describe the #, !, $ and [ ] symbols. for operand register identifiers, r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1 , r2, etc.) can be used for description. table 21-1. operand identifi ers and description methods identifier description method r rp sfr x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) ax (rp0), bc (rp1), de (rp2), hl (rp3) special function register symbol saddr saddrp fe20h to ff1fh immediate data or labels fe20h to ff1fh immediate data or labels (even addresses only) addr16 addr5 0000h to ffffh immediate data or labels (only ev en addresses for 16-bit data transfer instructions) 0040h to 007fh immediate data or labels (even addresses only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label remark for symbols of special function registers, see table 3-3 special function registers . chapter 21 instruction set overview user?s manual u17446ej5v0ud 335 21.1.2 description of ?operation? column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag ie: interrupt request enable flag ( ): memory contents indicated by addre ss or register contents in parentheses h , l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive logical sum (exclusive or) ? : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 21.1.3 description of ?flag? column (blank): unchanged 0: cleared to 0 1: set to 1 : set/cleared according to the result r: previously saved value is stored chapter 21 instruction set overview user?s manual u17446ej5v0ud 336 21.2 operation list flag mnemonic operand byte s clocks operation z ac cy r, #byte 3 6 r byte saddr, #byte 3 6 (saddr) byte sfr, #byte 3 6 sfr byte a, r note 1 2 4 a r r, a note 1 2 4 r a a, saddr 2 4 a (saddr) saddr, a 2 4 (saddr) a a, sfr 2 4 a sfr sfr, a 2 4 sfr a a, !addr16 3 8 a (addr16) !addr16, a 3 8 (addr16) a psw, #byte 3 6 psw byte a, psw 2 4 a psw psw, a 2 4 psw a a, [de] 1 6 a (de) [de], a 1 6 (de) a a, [hl] 1 6 a (hl) [hl], a 1 6 (hl) a a, [hl + byte] 2 6 a (hl + byte) mov [hl + byte], a 2 6 (hl + byte) a a, x 1 4 a ? x a, r note 2 2 6 a ? r a, saddr 2 6 a ? (saddr) a, sfr 2 6 a ? sfr a, [de] 1 8 a ? (de) a, [hl] 1 8 a ? (hl) xch a, [hl, byte] 2 8 a ? (hl + byte) notes 1. except r = a. 2. except r = a, x. remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). chapter 21 instruction set overview user?s manual u17446ej5v0ud 337 flag mnemonic operand byte s clocks operation z ac cy rp, #word 3 6 rp word ax, saddrp 2 6 ax (saddrp) saddrp, ax 2 8 (saddrp) ax ax, rp note 1 4 ax rp movw rp, ax note 1 4 rp ax xchw ax, rp note 1 8 ax ? rp a, #byte 2 4 a, cy a + byte saddr, #byte 3 6 (saddr), cy (saddr) + byte a, r 2 4 a, cy a + r a, saddr 2 4 a, cy a + (saddr) a, !addr16 3 8 a, cy a + (addr16) a, [hl] 1 6 a, cy a + (hl) add a, [hl + byte] 2 6 a, cy a + (hl + byte) a, #byte 2 4 a, cy a + byte + cy saddr, #byte 3 6 (saddr), cy (saddr) + byte + cy a, r 2 4 a, cy a + r + cy a, saddr 2 4 a, cy a + (saddr) + cy a, !addr16 3 8 a, cy a + (addr16) + cy a, [hl] 1 6 a, cy a + (hl) + cy addc a, [hl + byte] 2 6 a, cy a + (hl + byte) + cy a, #byte 2 4 a, cy a ? byte saddr, #byte 3 6 (saddr), cy (saddr) ? byte a, r 2 4 a, cy a ? r a, saddr 2 4 a, cy a ? (saddr) a, !addr16 3 8 a, cy a ? (addr16) a, [hl] 1 6 a, cy a ? (hl) sub a, [hl + byte] 2 6 a, cy a ? (hl + byte) note only when rp = bc, de, or hl. remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). chapter 21 instruction set overview user?s manual u17446ej5v0ud 338 flag mnemonic operand byte s clocks operation z ac cy a, #byte 2 4 a, cy a ? byte ? cy saddr, #byte 3 6 (saddr), cy (saddr) ? byte ? cy a, r 2 4 a, cy a ? r ? cy a, saddr 2 4 a, cy a ? (saddr) ? cy a, !addr16 3 8 a, cy a ? (addr16) ? cy a, [hl] 1 6 a, cy a ? (hl) ? cy subc a, [hl + byte] 2 6 a, cy a ? (hl + byte) ? cy a, #byte 2 4 a a byte saddr, #byte 3 6 (saddr) (saddr) byte a, r 2 4 a a r a, saddr 2 4 a a (saddr) a, !addr16 3 8 a a (addr16) a, [hl] 1 6 a a (hl) and a, [hl + byte] 2 6 a a (hl + byte) a, #byte 2 4 a a byte saddr, #byte 3 6 (saddr) (saddr) byte a, r 2 4 a a r a, saddr 2 4 a a (saddr) a, !addr16 3 8 a a (addr16) a, [hl] 1 6 a a (hl) or a, [hl + byte] 2 6 a a (hl + byte) a, #byte 2 4 a a byte saddr, #byte 3 6 (saddr) (saddr) byte a, r 2 4 a a r a, saddr 2 4 a a (saddr) a, !addr16 3 8 a a (addr16) a, [hl] 1 6 a a (hl) xor a, [hl + byte] 2 6 a a (hl + byte) remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). chapter 21 instruction set overview user?s manual u17446ej5v0ud 339 flag mnemonic operand byte s clocks operation z ac cy a, #byte 2 4 a ? byte saddr, #byte 3 6 (saddr) ? byte a, r 2 4 a ? r a, saddr 2 4 a ? (saddr) a, !addr16 3 8 a ? (addr16) a, [hl] 1 6 a ? (hl) cmp a, [hl + byte] 2 6 a ? (hl + byte) addw ax, #word 3 6 ax, cy ax + word subw ax, #word 3 6 ax, cy ax ? word cmpw ax, #word 3 6 ax ? word r 2 4 r r + 1 inc saddr 2 4 (saddr) (saddr) + 1 r 2 4 r r ? 1 dec saddr 2 4 (saddr) (saddr) ? 1 incw rp 1 4 rp rp + 1 decw rp 1 4 rp rp ? 1 ror a, 1 1 2 (cy, a 7 a 0 , a m ? 1 a m ) 1 rol a, 1 1 2 (cy, a 0 a 7 , a m+1 a m ) 1 rorc a, 1 1 2 (cy a 0 , a 7 cy, a m ? 1 a m ) 1 rolc a, 1 1 2 (cy a 7 , a 0 cy, a m+1 a m ) 1 saddr.bit 3 6 (saddr.bit) 1 sfr.bit 3 6 sfr.bit 1 a.bit 2 4 a.bit 1 psw.bit 3 6 psw.bit 1 set1 [hl].bit 2 10 (hl).bit 1 saddr.bit 3 6 (saddr.bit) 0 sfr.bit 3 6 sfr.bit 0 a.bit 2 4 a.bit 0 psw.bit 3 6 psw.bit 0 clr1 [hl].bit 2 10 (hl).bit 0 set1 cy 1 2 cy 1 1 clr1 cy 1 2 cy 0 0 not1 cy 1 2 cy cy remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). chapter 21 instruction set overview user?s manual u17446ej5v0ud 340 flag mnemonic operand byte s clocks operation z ac cy call !addr16 3 6 (sp ? 1) (pc + 3) h , (sp ? 2) (pc + 3) l , pc addr16, sp sp ? 2 callt [addr5] 1 8 (sp ? 1) (pc + 1) h , (sp ? 2) (pc + 1) l , pc h (00000000, addr5 + 1), pc l (00000000, addr5), sp sp ? 2 ret 1 6 pc h (sp + 1), pc l (sp), sp sp + 2 reti 1 8 pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3 r r r psw 1 2 (sp ? 1) psw, sp sp ? 1 push rp 1 4 (sp ? 1) rp h , (sp ? 2) rp l , sp sp ? 2 psw 1 4 psw (sp), sp sp + 1 r r r pop rp 1 6 rp h (sp + 1), rp l (sp), sp sp + 2 sp, ax 2 8 sp ax movw ax, sp 2 6 ax sp !addr16 3 6 pc addr16 $addr16 2 6 pc pc + 2 + jdisp8 br ax 1 6 pc h a, pc l x bc $saddr16 2 6 pc pc + 2 + jdisp8 if cy = 1 bnc $saddr16 2 6 pc pc + 2 + jdisp8 if cy = 0 bz $saddr16 2 6 pc pc + 2 + jdisp8 if z = 1 bnz $saddr16 2 6 pc pc + 2 + jdisp8 if z = 0 saddr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 1 bt psw.bit, $addr16 4 10 pc pc + 4 + jdisp8 if psw.bit = 1 saddr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 0 bf psw.bit, $addr16 4 10 pc pc + 4 + jdisp8 if psw.bit = 0 b, $addr16 2 6 b b ? 1, then pc pc + 2 + jdisp8 if b 0 c, $addr16 2 6 c c ? 1, then pc pc + 2 + jdisp8 if c 0 dbnz saddr, $addr16 3 8 (saddr) (saddr) ? 1, then pc pc + 3 + jdisp8 if (saddr) 0 nop 1 2 no operation ei 3 6 ie 1 (enable interrupt) di 3 6 ie 0 (disable interrupt) halt 1 2 set halt mode stop 1 2 set stop mode remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). chapter 21 instruction set overview user?s manual u17446ej5v0ud 341 21.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, inc, dec, ror, rol, rorc, rolc, push, pop, dbnz 2nd operand 1st operand #byte a r sfr saddr ! addr16 psw [de] [hl] [hl + byte] $addr16 1 none a add addc sub subc and or xor cmp mov note xch note add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc r mov mov inc dec b, c dbnz sfr mov mov saddr mov add addc sub subc and or xor cmp mov dbnz inc dec !addr16 mov psw mov mov push pop [de] mov [hl] mov [hl + byte] mov note except r = a. chapter 21 instruction set overview user?s manual u17446ej5v0ud 342 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw 2nd operand 1st operand #word ax rp note saddrp sp none ax addw subw cmpw movw xchw movw movw rp movw movw note incw decw push pop saddrp movw sp movw note only when rp = bc, de, or hl. (3) bit manipulation instructions set1, clr1, not1, bt, bf 2nd operand 1st operand $addr16 none a.bit bt bf set1 clr1 sfr.bit bt bf set1 clr1 saddr.bit bt bf set1 clr1 psw.bit bt bf set1 clr1 [hl].bit set1 clr1 cy set1 clr1 not1 chapter 21 instruction set overview user?s manual u17446ej5v0ud 343 (4) call instructions/branch instructions call, callt, br, bc, bnc, bz, bnz, dbnz 2nd operand 1st operand ax !addr16 [addr5] $addr16 basic instructions br call br callt br bc bnc bz bnz compound instructions dbnz (5) other instructions ret, reti, nop, ei, di, halt, stop user?s manual u17446ej5v0ud 344 chapter 22 electrical specifications (standard product, (a) grade product) absolute maximum ratings (t a = 25 c ) parameter symbol conditions ratings unit v dd ? 0.3 to +6.5 v v ss ? 0.3 to +0.3 v av ref ? 0.3 to v dd + 0.3 note v supply voltage av ss ? 0.3 to +0.3 v v i1 p00 to p03, p30 to p34, p40 to p47, p120 to p123 ? 0.3 to v dd + 0.3 note v input voltage v i2 p20 to p23 ? 0.3 to av ref + 0.3 note and ? 0.3 to v dd + 0.3 note v output voltage v o ? 0.3 to v dd + 0.3 note v analog input voltage v an ? 0.3 to av ref + 0.3 note and ? 0.3 to v dd + 0.3 note v per pin ? 10.0 ma total of pins other than p20 to p23 ? 44.0 ma output current, high i oh total of p20 to p23 ? 44.0 ma per pin 20.0 ma total of pins other than p20 to p23 44.0 ma output current, low i ol total of p20 to p23 44.0 ma in normal operation mode operating ambient temperature t a during flash memory programming ? 40 to +85 c flash memory blank status ? 65 to +150 c storage temperature t stg flash memory programming already performed ? 40 to +125 c note must be 6.5 v or lower caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute m aximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. chapter 22 electrical specifications (standard product, (a) grade product) user?s manual u17446ej5v0ud 345 standard product, (a) grade product t a = ? 40 to +85 c x1 oscillator characteristics (t a = ? 40 to +85 c, v dd = 2.0 to 5.5 v note 1 , v ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit ceramic resonator x2 x1 v ss c2 c1 oscillation frequency (f x ) note 2 2.0 10.0 mhz crystal resonator x2 x1 v ss c2 c1 oscillation frequency (f x ) note 2 2.0 10.0 mhz 2.7 v v dd 5.5 v 2.0 10.0 x1 input frequency (f x ) note 2 2.0 v v dd < 2.7 v 2.0 5.0 mhz 2.7 v v dd 5.5 v 0.045 0.25 external clock x1 x1 input high- /low-level width (t xh , t xl ) 2.0 v v dd < 2.7 v 0.09 0.25 s notes 1. use this product in a voltage range of 2.2 to 5.5 v because the detection voltage (v poc ) of the power-on- clear (poc) circuit is 2.1 v 0.1 v. 2. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. caution when using the x1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse eff ect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. remark for the resonator selection and oscillator constant, us ers are required to either evaluate the oscillation themselves or apply to the resonat or manufacturer for evaluation. chapter 22 electrical specifications (standard product, (a) grade product) user?s manual u17446ej5v0ud 346 standard product, (a) grade product t a = ? 40 to +85 c high-speed internal osc illator characteristics (t a = ? 40 to +85 c, v dd = 2.0 to 5.5 v note 1 , v ss = 0 v) resonator parameter conditions min. typ. max. unit t a = ? 10 to +80 c 3 % oscillation frequency (f x = 8 mhz note 2 ) deviation 2.7 v v dd 5.5 v t a = ? 40 to +85 c 5 % high-speed internal oscillator oscillation frequency (f x ) note 2 2.0 v v dd < 2.7 v 5.5 mhz notes 1. use this product in a voltage range of 2.2 to 5.5 v because the detection voltage (v poc ) of the power-on- clear (poc) circuit is 2.1 v 0.1 v. 2. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. low-speed internal osc illator characteristics (t a = ? 40 to +85 c, v dd = 2.0 to 5.5 v note , v ss = 0 v) resonator parameter conditions min. typ. max. unit low-speed internal oscillator oscillation frequency (f rl ) 120 240 480 khz note use this product in a voltage range of 2. 2 to 5.5 v because the detection voltage (v poc ) of the power-on-clear (poc) circuit is 2.1 v 0.1 v. chapter 22 electrical specifications (standard product, (a) grade product) user?s manual u17446ej5v0ud 347 standard product, (a) grade product t a = ? 40 to +85 c dc characteristics (t a = ? 40 to +85 c, v dd = 2.0 to 5.5 v note , v ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit per pin 2.0 v v dd 5.5 v ?5 ma 4.0 v v dd 5.5 v ?25 ma i oh1 pins other than p20 to p23 total 2.0 v v dd < 4.0 v ?15 ma per pin 2.0 v av ref 5.5 v ?5 ma output current, high i oh2 p20 to p23 total 2.0 v av ref 5.5 v ?15 ma per pin 2.0 v v dd 5.5 v 10 ma 4.0 v v dd 5.5 v 30 ma i ol1 pins other than p20 to p23 total 2.0 v v dd < 4.0 v 15 ma per pin 2.0 v av ref 5.5 v 10 ma 4.0 v av ref 5.5 v 30 ma output current, low i ol2 p20 to p23 total 2.0 v av ref < 4.0 v 15 ma v ih1 p00 to p03, p30 to p34, p40 to p47, p120, p123 0.8v dd v dd v v ih2 p20 to p23 0.7av ref av ref v input voltage, high v ih3 p121, p122 0.8v dd v dd v v il1 p00 to p03, p30 to p34, p40 to p47, p120, p123 0 0.2v dd v v il2 p20 to p23 0 0.3av ref v input voltage, low v il3 p121, p122 0 0.2v dd v total of pins other than p20 to p23 i oh1 = ?15 ma 4.0 v v dd 5.5 v i oh1 = ?5 ma v dd ? 1.0 v v oh1 i oh1 = ?100 a 2.0 v v dd < 4.0 v v dd ? 0.5 v total of pins p20 to p23 i oh2 = ?10 ma 4.0 v av ref 5.5 v i oh2 = ?5 ma av ref ? 1.0 v output voltage, high v oh2 2.0 v av ref < 4.0 v i oh2 = ?100 a av ref ? 0.5 v total of pins other than p20 to p23 i ol1 = 30 ma 4.0 v v dd 5.5 v i ol1 = 10 ma 1.3 v v ol1 i ol1 = 400 a 2.0 v v dd < 4.0 v 0.4 v total of pins p20 to p23 i ol2 = 30 ma 4.0 v av ref 5.5 v i ol2 = 10 ma 1.3 v output voltage, low v ol2 i ol2 = 400 a 2.0 v av ref < 4.0 v 0.4 v input leakage current, high i lih v i = v dd pins other than x1 1 a input leakage current, low i lil v i = 0 v pins other than x1 ?1 a output leakage current, high i loh v o = v dd pins other than x2 1 a output leakage current, low i lol v o = 0 v pins other than x2 ?1 a pull-up resistance r pu v i = 0 v 10 30 100 k pull-down resistance r pd p121, p122, reset status 10 30 100 k note use this product in a voltage range of 2. 2 to 5.5 v because the detection voltage (v poc ) of the power-on-clear (poc) circuit is 2.1 v 0.1 v. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. chapter 22 electrical specifications (standard product, (a) grade product) user?s manual u17446ej5v0ud 348 standard product, (a) grade product t a = ? 40 to +85 c dc characteristics (t a = ? 40 to +85 c, v dd = 2.0 to 5.5 v note 1 , v ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit when a/d converter is stopped 6.1 12.2 f x = 10 mhz v dd = 5.0 v 10% note 4 when a/d converter is operating note 8 7.6 15.2 ma when a/d converter is stopped 5.5 11.0 f x = 6 mhz v dd = 5.0 v 10% note 4 when a/d converter is operating note 8 14.0 ma when a/d converter is stopped 3.0 6.0 i dd1 note 3 crystal/ceramic oscillation, external clock input oscillation operating mode note 6 f x = 5 mhz v dd = 3.0 v 10% note 5 when a/d converter is operating note 8 4.5 9.0 ma when peripheral functions are stopped 1.7 3.8 f x = 10 mhz v dd = 5.0 v 10% note 4 when peripheral functions are operating 6.7 ma when peripheral functions are stopped 1.3 3.0 f x = 6 mhz v dd = 5.0 v 10% note 4 when peripheral functions are operating 6.0 ma when peripheral functions are stopped 0.48 1 i dd2 crystal/ceramic oscillation, external clock input halt mode note 6 f x = 5 mhz v dd = 3.0 v 10% note 5 when peripheral functions are operating 2.1 ma when a/d converter is stopped 5.0 10.0 i dd3 note 3 high-speed internal oscillation operating mode note 7 f x = 8 mhz v dd = 5.0 v 10% note 4 when a/d converter is operating note 8 6.5 13.0 ma when peripheral functions are stopped 1.4 3.2 i dd4 high-speed internal oscillation halt mode note 7 f x = 8 mhz v dd = 5.0 v 10% note 4 when peripheral functions are operating 5.9 ma when low-speed internal oscillation is stopped 3.5 20.0 v dd = 5.0 v 10% when low-speed internal oscillation is operating 17.5 32.0 a when low-speed internal oscillation is stopped 3.5 15.5 supply current note 2 i dd5 stop mode v dd = 3.0 v 10% when low-speed internal oscillation is operating 11.0 26.0 a notes 1. use this product in a voltage range of 2.2 to 5.5 v because the detection voltage (v poc ) of the power-on- clear (poc) circuit is 2.1 v 0.1 v. 2. total current flowing through the internal power supply (v dd ). peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). 3. peripheral operation current is included. 4. when the processor clock control register (pcc) is set to 00h. 5. when the processor clock control register (pcc) is set to 02h. 6. when crystal/ceramic oscillation clo ck, external clock input is select ed as the system clock source using the option byte. 7. when the high-speed internal oscillation clock is se lected as the system clock source using the option byte. 8. the current that flows through the av ref pin is included. chapter 22 electrical specifications (standard product, (a) grade product) user?s manual u17446ej5v0ud 349 standard product, (a) grade product t a = ? 40 to +85 c ac characteristics (1) basic operation (t a = ? 40 to +85 c, v dd = 2.0 to 5.5 v note 1 , v ss = 0 v) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 0.2 16 s 3.0 v v dd < 4.0 v 0.33 16 s 2.7 v v dd < 3.0 v 0.4 16 s crystal/ceramic oscillation clock, external clock input 2.0 v v dd < 2.7 v 1 16 s 4.0 v v dd 5.5 v 0.23 4.22 s 2.7 v v dd < 4.0 v 0.47 4.22 s cycle time (minimum instruction execution time) t cy high-speed internal oscillation clock 2.0 v v dd < 2.7 v 0.95 4.22 s 4.0 v v dd 5.5 v 2/fsam+ 0.1 note 2 s ti000 input high-level width, low-level width t tih , t til 2.0 v v dd < 4.0 v 2/fsam+ 0.2 note 2 s interrupt input high-level width, low-level width t inth , t intl 1 s reset input low-level width t rsl 2 s notes 1. use this product in a voltage range of 2.2 to 5.5 v because the detection voltage (v poc ) of the power-on- clear (poc) circuit is 2.1 v 0.1 v. 2. selection of fsam = f xp , f xp /4, or f xp /256 is possible using bits 0 and 1 (prm000, prm001) of prescaler mode register 00 (prm00). note that when selecting the valid edge of the ti000 pin as the count clock, fsam = f xp . cpu clock frequency, pe ripheral clock frequency parameter conditions cpu clock (f cpu ) peripheral clock (f xp ) 4.0 to 5.5 v 125 khz f cpu 10 mhz 3.0 to 4.0 v 125 khz f cpu 6 mhz 2.7 to 3.0 v 125 khz f cpu 5 mhz 500 khz f xp 10 mhz ceramic resonator, crystal resonator, external clock 2.0 to 2.7 v note 125 khz f cpu 2 mhz 500 khz f xp 5 mhz 4.0 to 5.5 v 500 khz (typ.) f cpu 8 mhz (typ.) 2.7 to 4.0 v 500 khz (typ.) f cpu 4 mhz (typ.) 2 mhz (typ.) f xp 8 mhz (typ.) high-speed internal oscillator 2.0 to 2.7 v note 500 khz (typ.) f cpu 2 mhz (typ.) 2 mhz (typ.) f xp 4 mhz (typ.) note use this product in a voltage range of 2. 2 to 5.5 v because the detection voltage (v poc ) of the power-on-clear (poc) circuit is 2.1 v 0.1 v. chapter 22 electrical specifications (standard product, (a) grade product) user?s manual u17446ej5v0ud 350 standard product, (a) grade product t a = ? 40 to +85 c t cy vs. v dd (crystal/ceramic o scillation clock, external clock input) supply voltage v dd [v] 123456 0.1 0.4 1.0 10 60 cycle time t cy [ s] guaranteed operation range 0.33 2.7 5.5 16 t cy vs. v dd (high-speed internal oscillator clock) 123456 0.1 1.0 10 60 2.7 5.5 0.23 4.22 0.47 0.95 supply voltage v dd [v] cycle time t cy [ s] guaranteed operation range chapter 22 electrical specifications (standard product, (a) grade product) user?s manual u17446ej5v0ud 351 standard product, (a) grade product t a = ? 40 to +85 c (2) serial interface (t a = ? 40 to +85 c, v dd = 2.0 to 5.5 v note , v ss = 0 v) uart mode (uart6, dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 312.5 kbps note use this product in a voltage range of 2. 2 to 5.5 v because the detection voltage (v poc ) of the power-on-clear (poc) circuit is 2.1 v 0.1 v. ac timing test points (excluding x1 input) 0.8v dd 0.2v dd 0.8v dd 0.2v dd test points clock timing 1/f x t xl t xh x1 input ti000 timing t til t tih ti000 interrupt input timing intp0 to intp3 t intl t inth reset input timing reset t rsl chapter 22 electrical specifications (standard product, (a) grade product) user?s manual u17446ej5v0ud 352 standard product, (a) grade product t a = ? 40 to +85 c a/d converter characteristics (t a = ? 40 to +85 c, 2.7 v av ref v dd 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit 4.0 v av ref 5.5 v 0.2 0.4 %fsr overall error notes 1, 2 ainl 2.7 v av ref < 4.0 v 0.3 0.6 %fsr 4.5 v av ref 5.5 v 3.0 100 s 4.0 v av ref < 4.5 v 4.8 100 s 2.85 v av ref < 4.0 v 6.0 100 s conversion time t conv 2.7 v av ref < 2.85 v 14.0 100 s 4.0 v av ref 5.5 v 0.4 %fsr zero-scale error notes 1, 2 ezs 2.7 v av ref < 4.0 v 0.6 %fsr 4.0 v av ref 5.5 v 0.4 %fsr full-scale error notes 1, 2 efs 2.7 v av ref < 4.0 v 0.6 %fsr 4.0 v av ref 5.5 v 2.5 lsb integral non-linearity error note 1 ile 2.7 v av ref < 4.0 v 4.5 lsb 4.0 v av ref 5.5 v 1.5 lsb differential non-linearity error note 1 dle 2.7 v av ref < 4.0 v 2.0 lsb analog input voltage v ain v ss av ref v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. caution the conversion accuracy may be degraded if the analog input pin is used as an alternate i/o port or if a port is changed during a/d conversion. chapter 22 electrical specifications (standard product, (a) grade product) user?s manual u17446ej5v0ud 353 standard product, (a) grade product t a = ? 40 to +85 c poc circuit characteristics (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit detection voltage v poc 2.0 2.1 2.2 v power supply boot time t pth v dd : 0 v 2.1 v 1.5 s response delay time 1 note 1 t pthd when power supply rises, after reaching detection voltage (max.) 3.0 ms response delay time 2 note 2 t pd when power supply falls 1.0 ms minimum pulse width t pw 0.2 ms notes 1. time required from voltage detection to internal reset release. 2. time required from voltage detection to internal reset signal generation. poc circuit timing supply voltage (v dd ) detection voltage (min.) detection voltage (typ.) detection voltage (max.) t pth t pthd t pw t pd time chapter 22 electrical specifications (standard product, (a) grade product) user?s manual u17446ej5v0ud 354 standard product, (a) grade product t a = ? 40 to +85 c lvi circuit characteristics (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit v lvi0 4.1 4.3 4.5 v v lvi1 3.9 4.1 4.3 v v lvi2 3.7 3.9 4.1 v v lvi3 3.5 3.7 3.9 v v lvi4 3.3 3.5 3.7 v v lvi5 3.15 3.3 3.45 v v lvi6 2.95 3.1 3.25 v v lvi7 2.7 2.85 3.0 v v lvi8 2.5 2.6 2.7 v detection voltage v lvi9 2.25 2.35 2.45 v response time note 1 t ld 0.2 2.0 ms minimum pulse width t lw 0.2 ms operation stabilization wait time note 2 t lwait 0.1 0.2 ms notes 1. time required from voltage detection to interr upt output or internal reset signal generation. 2. time required from setting lvion to 1 to operation stabilization. remarks 1. v lvi0 > v lvi1 > v lvi2 > v lvi3 > v lvi4 > v lvi5 > v lvi6 > v lvi7 > v lvi8 > v lvi9 2. v poc < v lvim (m = 0 to 9) lvi circuit timing supply voltage (v dd ) detection voltage (min.) detection voltage (typ.) detection voltage (max.) t lw t ld t lwait lvion 1 time data memory stop mode low supply vo ltage data retention characteristics (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 2.0 5.5 v release signal set time t srel 0 s chapter 22 electrical specifications (standard product, (a) grade product) user?s manual u17446ej5v0ud 355 standard product, (a) grade product t a = ? 40 to +85 c flash memory programming characteristics (t a = ?40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit supply current i dd v dd = 5.5 v 7.0 ma erasure count note 1 (per 1 block) n erase t a = ? 40 to +85 c 1000 times 4.5 v v dd 5.5 v 0.8 s 3.5 v v dd < 4.5 v 1.0 s t a = ? 10 to +85 c, n erase 100 2.7 v v dd < 3.5 v 1.2 s 4.5 v v dd 5.5 v 4.8 s 3.5 v v dd < 4.5 v 5.2 s t a = ? 10 to +85 c, n erase 1000 2.7 v v dd < 3.5 v 6.1 s 4.5 v v dd 5.5 v 1.6 s 3.5 v v dd < 4.5 v 1.8 s t a = ? 40 to +85 c, n erase 100 2.7 v v dd < 3.5 v 2.0 s 4.5 v v dd 5.5 v 9.1 s 3.5 v v dd < 4.5 v 10.1 s chip erase time t cerase t a = ? 40 to +85 c, n erase 1000 2.7 v v dd < 3.5 v 12.3 s 4.5 v v dd 5.5 v 0.4 s 3.5 v v dd < 4.5 v 0.5 s t a = ? 10 to +85 c, n erase 100 2.7 v v dd < 3.5 v 0.6 s 4.5 v v dd 5.5 v 2.6 s 3.5 v v dd < 4.5 v 2.8 s t a = ? 10 to +85 c, n erase 1000 2.7 v v dd < 3.5 v 2.3 s 4.5 v v dd 5.5 v 0.9 s 3.5 v v dd < 4.5 v 1.0 s t a = ? 40 to +85 c, n erase 100 2.7 v v dd < 3.5 v 1.1 s 4.5 v v dd 5.5 v 4.9 s 3.5 v v dd < 4.5 v 5.4 s block erase time t berase t a = ? 40 to +85 c, n erase 1000 2.7 v v dd < 3.5 v 6.6 s byte write time t write t a = ? 40 to +85 c, n erase 1000 150 s per 1 block 6.8 ms internal verify t verify per 1 byte 27 s blank check t blkchk per 1 block 480 s retention years t a = 85 c note 2 , n erase 1000 10 years note 1. depending on the erasure count (n erase ), the erase time varies. refer to the chip erase time and block erase time parameters. 2. when the average temperature when operating and not operating is 85 c. remark when a product is first written after shipment, ?erase write? and ?write only? ar e both taken as one rewrite. user?s manual u17446ej5v0ud 356 chapter 23 electrical spec ifications ((a2) grade product) absolute maximum ratings (t a = 25 c ) parameter symbol conditions ratings unit v dd ? 0.3 to +6.5 v v ss ? 0.3 to +0.3 v av ref ? 0.3 to v dd + 0.3 note 1 v supply voltage av ss ? 0.3 to +0.3 v v i1 p00 to p03, p30 to p34, p40 to p47, p120 to p123 ? 0.3 to v dd + 0.3 note 1 v input voltage v i2 p20 to p23 ? 0.3 to av ref + 0.3 note 1 and ? 0.3 to v dd + 0.3 note 1 v output voltage v o ? 0.3 to v dd + 0.3 note 1 v analog input voltage v an ? 0.3 to av ref + 0.3 note 1 and ? 0.3 to v dd + 0.3 note 1 v per pin ? 7.0 ma total of pins other than p20 to p23 ? 30.0 ma output current, high i oh total of p20 to p23 ? 30.0 ma per pin 14.0 ma total of pins other than p20 to p23 30.0 ma output current, low i ol total of p20 to p23 30.0 ma t a = ? 40 to +85 c 120 mw total loss p t note 2 t a = +85 to +125 c 110 mw in normal operation mode ? 40 to +125 c operating ambient temperature t a during flash memory programming ? 40 to +105 c flash memory blank status ? 65 to +150 c storage temperature t stg flash memory programming already performed ? 40 to +125 c note 1. must be 6.5 v or lower caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute m aximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. (note 2 is listed on the next page.) chapter 23 electrical specifications ((a2) grade product) user?s manual u17446ej5v0ud 357 (a2) grade product t a = ? 40 to +125 c note 2. this varies depending on the allowable total loss (see the figure below). ? 40 0 +40 +80 +85 temperature [?c] total loss p t [mw] +120 50 100 150 120 +125 110 use the following formula to perform design such that the sum of the power cons umption of the device is less than or equal to the total loss p t (use at 80% or less of the rated value is recommended). ? total power consumption = v dd {i dd ? i oh } + {(v dd ? v oh ) i oh } + (v ol i ol ) when guaranteeing the internal pull-up resistor, use the following formula to calculate its power consumption, and add the re sult to the result above. ? power consumption of internal pull-up resistor = (v dd /r pu v dd ) chapter 23 electrical specifications ((a2) grade product) user?s manual u17446ej5v0ud 358 (a2) grade product t a = ? 40 to +125 c x1 oscillator characteristics (t a = ? 40 to +125 c, v dd = 2.0 to 5.5 v note 1 , v ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit ceramic resonator x2 x1 v ss c2 c1 oscillation frequency (f x ) note 2 2.0 8.0 mhz crystal resonator x2 x1 v ss c2 c1 oscillation frequency (f x ) note 2 2.0 8.0 mhz 2.7 v v dd 5.5 v 2.0 8.0 x1 input frequency (f x ) note 2 2.0 v v dd < 2.7 v 2.0 5.0 mhz 2.7 v v dd 5.5 v 0.057 0.25 external clock x1 x1 input high- /low-level width (t xh , t xl ) 2.0 v v dd < 2.7 v 0.09 0.25 s notes 1. use this product in a voltage range of 2.26 to 5.5 v because the detection voltage (v poc ) of the power-on- clear (poc) circuit is 2.26 v (max.). 2. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. caution when using the x1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse eff ect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. remark for the resonator selection and oscillator constant, us ers are required to either evaluate the oscillation themselves or apply to the resonat or manufacturer for evaluation. chapter 23 electrical specifications ((a2) grade product) user?s manual u17446ej5v0ud 359 (a2) grade product t a = ? 40 to +125 c high-speed internal osc illator characteristics (t a = ? 40 to +125 c, v dd = 2.0 to 5.5 v note 1 , v ss = 0 v) resonator parameter conditions min. typ. max. unit t a = ? 10 to +80 c 3 % oscillation frequency (f x = 8 mhz note 2 ) deviation 2.7 v v dd 5.5 v t a = ? 40 to +125 c 5 % high-speed internal oscillator oscillation frequency (f x ) note 2 2.0 v v dd < 2.7 v 5.5 mhz notes 1. use this product in a voltage range of 2.26 to 5.5 v because the detection voltage (v poc ) of the power-on- clear (poc) circuit is 2.26 v (max.). 2. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. low-speed internal osc illator characteristics (t a = ? 40 to +125 c, v dd = 2.0 to 5.5 v note , v ss = 0 v) resonator parameter conditions min. typ. max. unit low-speed internal oscillator oscillation frequency (f rl ) 120 240 495 khz note use this product in a voltage range of 2.26 to 5.5 v because t he detection voltage (v poc ) of the power-on-clear (poc) circuit is 2.26 v (max.). chapter 23 electrical specifications ((a2) grade product) user?s manual u17446ej5v0ud 360 (a2) grade product t a = ? 40 to +125 c dc characteristics (t a = ? 40 to +125 c, v dd = 2.0 to 5.5 v note , v ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit per pin 2.0 v v dd 5.5 v ?3.5 ma 4.0 v v dd 5.5 v ?17.5 ma i oh1 pins other than p20 to p23 total 2.0 v v dd < 4.0 v ?10.5 ma per pin 2.0 v av ref 5.5 v ?3.5 ma output current, high i oh2 p20 to p23 total 2.0 v av ref 5.5 v ?10.5 ma per pin 2.0 v v dd 5.5 v 7.0 ma 4.0 v v dd 5.5 v 21.0 ma i ol1 pins other than p20 to p23 total 2.0 v v dd < 4.0 v 10.5 ma per pin 2.0 v av ref 5.5 v 7.0 ma 4.0 v av ref 5.5 v 21.0 ma output current, low i ol2 p20 to p23 total 2.0 v av ref < 4.0 v 10.5 ma v ih1 p00 to p03, p30 to p34, p40 to p47, p120, p123 0.8v dd v dd v v ih2 p20 to p23 0.7av ref av ref v input voltage, high v ih3 p121, p122 0.8v dd v dd v v il1 p00 to p03, p30 to p34, p40 to p47, p120, p123 0 0.2v dd v v il2 p20 to p23 0 0.3av ref v input voltage, low v il3 p121, p122 0 0.2v dd v total of pins other than p20 to p23 i oh1 = ?10.5 ma 4.0 v v dd 5.5 v i oh1 = ?3.5 ma v dd ? 1.0 v v oh1 i oh1 = ?100 a 2.0 v v dd < 4.0 v v dd ? 0.5 v total of pins p20 to p23 i oh2 = ?7 ma 4.0 v av ref 5.5 v i oh2 = ?3.5 ma av ref ? 1.0 v output voltage, high v oh2 2.0 v av ref < 4.0 v i oh2 = ?100 a av ref ? 0.5 v total of pins other than p20 to p23 i ol1 = 21 ma 4.0 v v dd 5.5 v i ol1 = 7 ma 1.3 v v ol1 2.0 v v dd < 4.0 v i ol1 = 400 a 0.4 v total of pins p20 to p23 i ol2 = 21 ma 4.0 v av ref 5.5 v i ol2 = 7 ma 1.3 v output voltage, low v ol2 2.0 v av ref < 4.0 v i ol2 = 400 a 0.4 v input leakage current, high i lih v i = v dd pins other than x1 10 a input leakage current, low i lil v i = 0 v pins other than x1 ?10 a output leakage current, high i loh v o = v dd pins other than x2 10 a output leakage current, low i lol v o = 0 v pins other than x2 ?10 a pull-up resistance r pu v i = 0 v 10 30 120 k pull-down resistance r pd p121, p122, reset status 10 30 120 k note use this product in a voltage range of 2. 26 to 5.5 v because the detection voltage (v poc ) of the power-on-clear (poc) circuit is 2.26 (max.). remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. chapter 23 electrical specifications ((a2) grade product) user?s manual u17446ej5v0ud 361 (a2) grade product t a = ? 40 to +125 c dc characteristics (t a = ? 40 to +125 c, v dd = 2.0 to 5.5 v note 1 , v ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit when a/d converter is stopped 5.8 12.8 f x = 8 mhz v dd = 5.0 v 10% note 4 when a/d converter is operating note 8 7.3 15.8 ma when a/d converter is stopped 5.5 12.2 f x = 6 mhz v dd = 5.0 v 10% note 4 when a/d converter is operating note 8 15.2 ma when a/d converter is stopped 3.0 6.6 i dd1 note 3 crystal/ceramic oscillation, external clock input oscillation operating mode note 6 f x = 5 mhz v dd = 3.0 v 10% note 5 when a/d converter is operating note 8 4.5 9.6 ma when peripheral functions are stopped 1.5 4.6 f x = 8 mhz v dd = 5.0 v 10% note 4 when peripheral functions are operating 7.6 ma when peripheral functions are stopped 1.3 4.2 f x = 6 mhz v dd = 5.0 v 10% note 4 when peripheral functions are operating 7.2 ma when peripheral functions are stopped 0.48 1.6 i dd2 crystal/ceramic oscillation, external clock input halt mode note 6 f x = 5 mhz v dd = 3.0 v 10% note 5 when peripheral functions are operating 2.7 ma when a/d converter is stopped 5.0 12.2 i dd3 note 3 high-speed internal oscillation operating mode note 7 f x = 8 mhz v dd = 5.0 v 10% note 4 when a/d converter is operating note 8 6.5 15.2 ma when peripheral functions are stopped 1.4 4.4 i dd4 high-speed internal oscillation halt mode note 7 f x = 8 mhz v dd = 5.0 v 10% note 4 when peripheral functions are operating 7.1 ma when low-speed internal oscillation is stopped 3.5 1200 v dd = 5.0 v 10% when low-speed internal oscillation is operating 17.5 1300 a when low-speed internal oscillation is stopped 3.5 600 supply current note 2 i dd5 stop mode v dd = 3.0 v 10% when low-speed internal oscillation is operating 11.0 700 a notes 1. use this product in a voltage range of 2.26 to 5.5 v because the detection voltage (v poc ) of the power-on- clear (poc) circuit is 2.26 v (max.). 2. total current flowing through the internal power supply (v dd ). peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). 3. peripheral operation current is included. 4. when the processor clock control register (pcc) is set to 00h. 5. when the processor clock control register (pcc) is set to 02h. 6. when crystal/ceramic oscillation clo ck, external clock input is select ed as the system clock source using the option byte. 7. when the high-speed internal oscillation clock is se lected as the system clock source using the option byte. 8. the current that flows through the av ref pin is included. chapter 23 electrical specifications ((a2) grade product) user?s manual u17446ej5v0ud 362 (a2) grade product t a = ? 40 to +125 c ac characteristics (1) basic operation (t a = ? 40 to +125 c, v dd = 2.0 to 5.5 v note 1 , v ss = 0 v) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 0.25 16 s 3.0 v v dd < 4.0 v 0.33 16 s 2.7 v v dd < 3.0 v 0.4 16 s crystal/ceramic oscillation clock, external clock input 2.0 v v dd < 2.7 v 1 16 s 4.0 v v dd 5.5 v 0.23 4.22 s 2.7 v v dd < 4.0 v 0.47 4.22 s cycle time (minimum instruction execution time) t cy high-speed internal oscillation clock 2.0 v v dd < 2.7 v 0.95 4.22 s 4.0 v v dd 5.5 v 2/fsam+ 0.1 note 2 s ti000 input high-level width, low-level width t tih , t til 2.0 v v dd < 4.0 v 2/fsam+ 0.2 note 2 s interrupt input high-level width, low-level width t inth , t intl 1 s reset input low-level width t rsl 2 s notes 1. use this product in a voltage range of 2.26 to 5.5 v because the detection voltage (v poc ) of the power-on- clear (poc) circuit is 2.26 v (max.). 2. selection of fsam = f xp , f xp /4, or f xp /256 is possible using bits 0 and 1 (prm000, prm001) of prescaler mode register 00 (prm00). note that when selecting the valid edge of the ti000 pin as the count clock, fsam = f xp . cpu clock frequency, pe ripheral clock frequency parameter conditions cpu clock (f cpu ) peripheral clock (f xp ) 4.0 to 5.5 v 125 khz f cpu 8 mhz 3.0 to 4.0 v 125 khz f cpu 6 mhz 2.7 to 3.0 v 125 khz f cpu 5 mhz 500 khz f xp 8 mhz ceramic resonator, crystal resonator, external clock 2.0 to 2.7 v note 125 khz f cpu 2 mhz 500 khz f xp 5 mhz 4.0 to 5.5 v 500 khz (typ.) f cpu 8 mhz (typ.) 2.7 to 4.0 v 500 khz (typ.) f cpu 4 mhz (typ.) 2 mhz (typ.) f xp 8 mhz (typ.) high-speed internal oscillator 2.0 to 2.7 v note 500 khz (typ.) f cpu 2 mhz (typ.) 2 mhz (typ.) f xp 4 mhz (typ.) note use this product in a voltage range of 2. 26 to 5.5 v because the detection voltage (v poc ) of the power-on-clear (poc) circuit is 2.26 v (max.). chapter 23 electrical specifications ((a2) grade product) user?s manual u17446ej5v0ud 363 (a2) grade product t a = ? 40 to +125 c t cy vs. v dd (crystal/ceramic o scillation clock, external clock input) supply voltage v dd [v] 123456 0.1 0.4 1.0 10 60 cycle time t cy [ s] guaranteed operation range 0.33 2.7 5.5 16 0.25 t cy vs. v dd (high-speed internal oscillator clock) 123456 0.1 1.0 10 60 2.7 5.5 0.23 4.22 0.47 0.95 supply voltage v dd [v] cycle time t cy [ s] guaranteed operation range chapter 23 electrical specifications ((a2) grade product) user?s manual u17446ej5v0ud 364 (a2) grade product t a = ? 40 to +125 c (2) serial interface (t a = ? 40 to +125 c, v dd = 2.0 to 5.5 v note , v ss = 0 v) uart mode (uart6, dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 312.5 kbps note use this product in a voltage range of 2. 26 to 5.5 v because the detection voltage (v poc ) of the power-on-clear (poc) circuit is 2.26 v (max.). ac timing test points (excluding x1 input) 0.8v dd 0.2v dd 0.8v dd 0.2v dd test points clock timing 1/f x t xl t xh x1 input ti000 timing t til t tih ti000 interrupt input timing intp0 to intp3 t intl t inth reset input timing reset t rsl chapter 23 electrical specifications ((a2) grade product) user?s manual u17446ej5v0ud 365 (a2) grade product t a = ? 40 to +125 c a/d converter characteristics (t a = ? 40 to +125 c, 2.7 v av ref v dd 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit 4.0 v av ref 5.5 v 0.2 0.7 %fsr overall error notes 1, 2 ainl 2.7 v av ref < 4.0 v 0.3 0.9 %fsr 4.5 v av ref 5.5 v 3.0 30 s 4.0 v av ref < 4.5 v 4.8 30 s 2.85 v av ref < 4.0 v 6.0 30 s conversion time t conv 2.7 v av ref < 2.85 v 14.0 30 s 4.0 v av ref 5.5 v 0.7 %fsr zero-scale error notes 1, 2 ezs 2.7 v av ref < 4.0 v 0.9 %fsr 4.0 v av ref 5.5 v 0.7 %fsr full-scale error notes 1, 2 efs 2.7 v av ref < 4.0 v 0.9 %fsr 4.0 v av ref 5.5 v 5.5 lsb integral non-linearity error note 1 ile 2.7 v av ref < 4.0 v 7.5 lsb 4.0 v av ref 5.5 v 2.5 lsb differential non-linearity error note 1 dle 2.7 v av ref < 4.0 v 3.0 lsb analog input voltage v ain v ss av ref v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. caution the conversion accuracy may be degraded if the analog input pin is used as an alternate i/o port or if a port is changed during a/d conversion. chapter 23 electrical specifications ((a2) grade product) user?s manual u17446ej5v0ud 366 (a2) grade product t a = ? 40 to +125 c poc circuit characteristics (t a = ? 40 to +125 c) parameter symbol conditions min. typ. max. unit detection voltage v poc 2.0 2.1 2.26 v power supply boot time t pth v dd : 0 v 2.1 v 1.5 s response delay time 1 note 1 t pthd when power supply rises, after reaching detection voltage (max.) 3.0 ms response delay time 2 note 2 t pd when power supply falls 1.0 ms minimum pulse width t pw 0.2 ms notes 1. time required from voltage detection to internal reset release. 2. time required from voltage detection to internal reset signal generation. poc circuit timing supply voltage (v dd ) detection voltage (min.) detection voltage (typ.) detection voltage (max.) t pth t pthd t pw t pd time chapter 23 electrical specifications ((a2) grade product) user?s manual u17446ej5v0ud 367 (a2) grade product t a = ? 40 to +125 c lvi circuit characteristics (t a = ? 40 to +125 c) parameter symbol conditions min. typ. max. unit v lvi0 4.1 4.3 4.65 v v lvi1 3.9 4.1 4.45 v v lvi2 3.7 3.9 4.25 v v lvi3 3.5 3.7 4.05 v v lvi4 3.3 3.5 3.85 v v lvi5 3.15 3.3 3.60 v v lvi6 2.95 3.1 3.40 v v lvi7 2.70 2.85 3.15 v v lvi8 2.50 2.60 2.85 v detection voltage v lvi9 2.25 2.35 2.60 v response time note 1 t ld 0.2 2.0 ms minimum pulse width t lw 0.2 ms operation stabilization wait time note 2 t lwait 0.1 0.2 ms notes 1. time required from voltage detection to interr upt output or internal reset signal generation. 2. time required from setting lvion to 1 to operation stabilization. remarks 1. v lvi0 > v lvi1 > v lvi2 > v lvi3 > v lvi4 > v lvi5 > v lvi6 > v lvi7 > v lvi8 > v lvi9 2. v poc < v lvim (m = 0 to 9) lvi circuit timing supply voltage (v dd ) detection voltage (min.) detection voltage (typ.) detection voltage (max.) t lw t ld t lwait lvion 1 time data memory stop mode low supply vo ltage data retention characteristics (t a = ? 40 to +125 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 2.0 5.5 v release signal set time t srel 0 s chapter 23 electrical specifications ((a2) grade product) user?s manual u17446ej5v0ud 368 (a2) grade product t a = ? 40 to +125 c flash memory programming characteristics (t a = ?40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit supply current i dd v dd = 5.5 v 7.0 ma erasure count note 1 (per 1 block) n erase t a = ? 40 to +105 c 1000 times 4.5 v v dd 5.5 v 0.8 s 3.5 v v dd < 4.5 v 1.0 s t a = ? 10 to +105 c, n erase 100 2.7 v v dd < 3.5 v 1.2 s 4.5 v v dd 5.5 v 4.8 s 3.5 v v dd < 4.5 v 5.2 s t a = ? 10 to +105 c, n erase 1000 2.7 v v dd < 3.5 v 6.1 s 4.5 v v dd 5.5 v 1.6 s 3.5 v v dd < 4.5 v 1.8 s t a = ? 40 to +105 c, n erase 100 2.7 v v dd < 3.5 v 2.0 s 4.5 v v dd 5.5 v 9.1 s 3.5 v v dd < 4.5 v 10.1 s chip erase time t cerase t a = ? 40 to +105 c, n erase 1000 2.7 v v dd < 3.5 v 12.3 s 4.5 v v dd 5.5 v 0.4 s 3.5 v v dd < 4.5 v 0.5 s t a = ? 10 to +105 c, n erase 100 2.7 v v dd < 3.5 v 0.6 s 4.5 v v dd 5.5 v 2.6 s 3.5 v v dd < 4.5 v 2.8 s t a = ? 10 to +105 c, n erase 1000 2.7 v v dd < 3.5 v 3.3 s 4.5 v v dd 5.5 v 0.9 s 3.5 v v dd < 4.5 v 1.0 s t a = ? 40 to +105 c, n erase 100 2.7 v v dd < 3.5 v 1.1 s 4.5 v v dd 5.5 v 4.9 s 3.5 v v dd < 4.5 v 5.4 s block erase time t berase t a = ? 40 to +105 c, n erase 1000 2.7 v v dd < 3.5 v 6.6 s byte write time t write t a = ? 40 to +105 c, n erase 1000 150 s per 1 block 6.8 ms internal verify t verify per 1 byte 27 s blank check t blkchk per 1 block 480 s total loss p t note 3 t a = ? 40 to +105 c 120 mw retention years t a = 85 c note 2 , n erase 1000 10 years notes 1. depending on the erasure count (n erase ), the erase time varies. refer to the chip erase time and block erase time parameters. 2. when the average temperature when operating and not operating is 85 c. remark when a product is first written after shipment, ?erase write? and ?write only? ar e both taken as one rewrite. (note 3 is listed on the next page.) chapter 23 electrical specifications ((a2) grade product) user?s manual u17446ej5v0ud 369 (a2) grade product t a = ? 40 to +125 c note 3. when guaranteeing the flash self pr ogramming, use the following formula to perform design such that the sum of the power consumpti on of the device is less than or equal to the total loss p t (use at 80% or less of the rated value is recommended). ? total power consumption = v dd {i dd ? i oh } + {(v dd ? v oh ) i oh } + (v ol i ol ) when guaranteeing the internal pull-up resistor, use the following formula to calculate its power consumption, and add the re sult to the result above. ? power consumption of internal pull-up resistor = (v dd /r pu v dd ) remark during flash memory programming, i dd = 7.0 ma (max.). user?s manual u17446ej5v0ud 370 chapter 24 package drawing ? pd78f9232mc-5a4-a, 78f9234mc-5a4-a, 78f9232m c(a)-5a4-a, 78f9234mc(a)-5a4-a, 78f9232mc(a2)-5a4-a, 78f9234mc(a2)-5a4-a s s h j t i g d e f c b k p l u n item b c i l m n 30-pin plastic ssop (7.62 mm (300)) a k d e f g h j p 30 16 115 a detail of lead end m m t millimeters 0.65 (t.p.) 0.45 max. 0.13 0.5 6.1 0.2 0.10 9.85 0.15 0.17 0.03 0.1 0.05 0.24 1.3 0.1 8.1 0.2 1.2 + 0.08 ? 0.07 1.0 0.2 3 + 5 ? 3 0.25 0.6 0.15 u note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. s30mc-65-5a4-2 chapter 24 package drawing user?s manual u17446ej5v0ud 371 ? pd78f9232mc(a)-cab-ax, 78f9234mc(a)-cab-ax, 78f9232mc(a2)-cab-ax, 78f9234mc(a2)-cab-ax 16 30 1 m s s v 30-pin plastic ssop (7.62mm (300)) detail of lead end note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item dimensions a b c e f g h i j l m n d 0.30 0.65 (t.p.) 0.10 0.05 1.30 0.10 1.20 8.10 0.20 6.10 0.10 1.00 0.20 0.50 0.13 0.10 0.22 + 0.10 ? 0.05 k 0.15 + 0.05 ? 0.01 p 3 + 5 ? 3 (unit:mm) p30mc-65-cab v w w a i f g e c n d m b k h j p u t l 9.70 0.10 t u v 0.25(t.p.) 0.60 0.15 0.25 max. w 0.15 max. 15 chapter 24 package drawing user?s manual u17446ej5v0ud 372 ? pd78f9232cs-caa-a, 78f9234cs-caa-a 32-pin plastic sdip (7.62mm(300)) item dimensions d e e1 c l x z 0 to 15 p32cs-70-caa z a2 a l b b1 b2 32 17 1 16 m a1 b2 xc ab b1 b c 28.05 0.15 6.60 0.20 3.45 0.15 + 0.65 0.50 1.02 0.75 2.86 0.25 2.80 1.778 7.62 0.25 0.615 0.10 0.10 0.10 0.10 0.20 0.10 0.05 e a a1 a2 d e b (unit:mm) e1 e c a user?s manual u17446ej5v0ud 373 chapter 25 recommended soldering conditions these products should be soldered and mount ed under the following recommended conditions. for technical information, see the following website. semiconductor device mount manual (h ttp://www.necel.com/pkg/en/mount/index.html) cautions 1. products with ?a or ?ax at the end of the part numbe r are lead-free products. 2. for soldering methods and conditions other than those reco mmended below, contact an nec electronics sales representative. table 25-1. surface mounting type soldering cond itions (1/2) ? 30-pin plastic ssop (lead-free products) pd78f9232mc-5a4-a, 78f9234mc-5a4-a, 78f 9232mc(a)-5a4-a, 78f9234mc(a)-5a4-a, 78f9232mc(a2)-5a4-a, 78f9234mc(a2)-5a4-a soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. (at 220 c or higher), count: 3 times or less, exposure limit: 7 days note (after that, prebake at 125 c for 20 to 72 hours) ir60-207-3 wave soldering for details, contact an nec electronics sales representative. ? partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together ( except for partial heating). chapter 25 recommended soldering conditions user?s manual u17446ej5v0ud 374 table 25-1. surface mounting type soldering cond itions (2/2) ? 30-pin plastic ssop (lead-free products) pd78f9232mc(a)-cab-ax, 78f9234mc(a )-cab-ax, 78f9232mc(a2)-cab-ax, 78f9234mc(a2)-cab-ax soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. (at 220 c or higher), count: 3 times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 to 72 hours) ir60-107-3 wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, preheating temperature: 120 c max. (package surface temperature), exposure limit: 7 days note (after that, prebake at 125 c for 10 to 72 hours) ws60-107-1 partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together ( except for partial heating). ? 32-pin plastic sdip (lead-free products) pd78f9232cs-caa-a, 78f9234cs-caa-a soldering method soldering conditions recommended condition symbol wave soldering (only for pins) solder bath temperature: 260 c max., time: 10 seconds max. ? partial heating pin temperature: 350 c max., time: 3 seconds max. (per one pin) ? caution only the pins of the thd are h eated when performing wave soldering. make sure that flow solder does not come in contact with the package. user?s manual u17446ej5v0ud 375 appendix a development tools the following development tools are available for development of systems usi ng the 78k0s/kb1+. figure a-1 shows the developm ent tool configuration. appendix a development tools user?s manual u17446ej5v0ud 376 figure a-1. development tool configuration (1/2) (1) when using the in-circuit emulator qb-78k0skx1 language processing software debugging software host machine (pc or ews) qb-78k0skx1 note 4 emulation probe target system software package control software (windows only) note 3 power supply unit usb interface cable note 4 78k0/kx1+ flash memory programmer note 4 flash memory write adapter < flash memory write environment > conversion adapter on-board programming off-board programming target connector assembler package c compiler package device file note 1 integrated debugger note 1 system simulator note 2 software package project manager notes 1. download the device file for 78k0s/kx1+ microc ontrollers (df789234) and the integrated debugger id78k0s-qb from the download site for developm ent tools (http://www.nece l.com/micro/en/ods/). 2. sm+ for 78k0s (instruction simulation version) is included in the software package. sm+ for 78k0s/kx1+ (instruction + peripheral simulation version) is not included. 3. the project manager pm+ is in cluded in the assembler package. pm+ cannot be used other than with windows tm . 4. qb-78k0skx1 is supplied with the integrated debugger id78k0s-qb, a usb interface cable, the on- chip debug emulator with programming function qb-mi ni2, a connection cable, and a target cable. any other products are sold separately. appendix a development tools user?s manual u17446ej5v0ud 377 figure a-1. development tools (2/2) (2) when using the on-chip debug emulat or with programming function qb-mini2 language processing software debugging software host machine (pc or ews) usb interface cable note 4 target connector target system software package control software (windows only) note 3 qb-mini2 note 4 connection cable note 4 ? assembler package ? c compiler package ? device file note 1 ? integrated debugger note 1 ? system simulator note 2 ? software package ? project manager notes 1. download the device file for 78k0s/kx1+ microc ontrollers (df789234) and the integrated debugger id78k0s-qb from the download site for developm ent tools (http://www.nece l.com/micro/en/ods/). 2. sm+ for 78k0s (instruction simulation version) is included in the software package. sm+ for 78k0s/kx1+ (instruction + peripheral simulation version) is not included. 3. the project manager pm+ is in cluded in the assembler package. pm+ cannot be used other than with windows. 4. qb-mini2 is supplied with usb interface cable and connection cable. any other products are sold separately. in addition, download the software fo r operating the qb-mini2 from the download site for development tools (http://www.nec el.com/micro/en/ods/). appendix a development tools user?s manual u17446ej5v0ud 378 a.1 software package sp78k0s 78k0s microcontroller software package development tools (software) common to the 78k0s microcontrollers are combined in this package. a.2 language processing software ra78k0s note 1 assembler package this assembler converts programs written in m nemonics into object codes executable with a microcontroller. this assembler is also provided with functions capable of automatically creating symbol tables and branch instruction optimization. this assembler should be used in combination with a device file (df789234). appendix a development tools user?s manual u17446ej5v0ud 379 a.3 flash memory writing tools a.3.1 when using flash memory programmer pg-fp5 and fl-pr5 fl-pr5, pg-fp5 flash memory programmer this is a flash memory programmer dedicat ed to microcontrollers incorporating a flash memory. fa-78f9234mc-5a4-rx flash memory writing adapter this is a flash memory writing adapter wh ich is used in connection with the flash memory programmer. remarks 1. fl-pr5 and fa-78f9234mc-5a4-rx are products of naito densei machida mfg. co., ltd (http://www.ndk-m.co.jp/, e-ma il: info@ndk-m.co.jp). 2. use the latest version of the flash memory programming adapter. a.3.2 when using on-chip debug emul ator with programming function qb-mini2 qb-mini2 on-chip debug emulator with programming function this is a flash memory programmer dedicat ed to microcontrollers with on-chip flash memory. it is available also as on-chip debug emulator which serves to debug hardware and software when developing application systems using the 78k0s/kx1+ microcontrollers. when using this as flash memory programmer, it should be used in combination with a connection cable and a usb interface cable that is used to connect the host machine. target connector specific ations 16-pin general-purpose connector (2.54 mm pitch) remark download the software for operating the qb-mini2 from the download site for development tools (http://www.necel.com/micro/en/ods/). a.4 debugging tools (hardware) a.4.1 when using in-circu it emulator qb-78k0skx1 qb-78k0skx1 in-circuit emulator this in-circuit emulator serves to debug har dware and software when developing application systems using the 78k0s/kx1+ microcontrollers. it supports the integrated debugger (id78k0s-qb). this emulator should be used in combination with a power supply unit and emulation probe, and the usb is used to conn ect this emulator to the host machine. qb-50-ep-01t note emulation probe this is a flexible type emulation probe and is used to connect the in-circuit emulator and target system. qb-30mc-ea-04t note exchange adapter this exchange adapter is used to perform pin conver sion from the in-circuit emulator to target connector. qb-30mc -nq-02t note target connector this target connector is used to mount on the target system. specifications of pin header on target system 0.635 mm 0.635 mm (height: 6 mm) (note and remarks are listed on the next page or later.) appendix a development tools user?s manual u17446ej5v0ud 380 note the part numbers of the exchange ada pter and target connector and the packages of the target device are described below. package exchange adapter target connector 30-pin plastic ssop (mc-5a4 and mc-cab types) qb-30mc-ea-04t qb-30mc-nq-02t 32-pin plastic sdip (cs-caa type) none none remarks 1. for the sdip package, use the target cable. 2. the qb-78k0skx1 is supplied wit h the integrated debugger id78k0s-q b, a usb interface cable, the on-chip debug emulator qb-mini 2, and a connection cable. download the software for operating the qb-mini 2 from the download site for development tools (http://www.necel.com/micro/en/ods /) when using the qb-mini2. 3. the packed contents of qb-78k0skx1 diffe r depending on the part number, as follows. packed contents part number in-circuit emulator emulation probe exchange adapter target connector qb-78k0skx1-zzz none qb-78k0skx1-t30mc qb-78k0skx1 qb-50-ep-01t qb-30mc-ea-04t qb-30mc-nq-02t a.4.2 when using on-chip debug emul ator with programming function qb-mini2 qb-mini2 on-chip debug emulator with programming function this on-chip debug emulator serves to debug hardware and software when developing application systems using the 78k0s/kx1+ microc ontrollers. it is available also as flash memory programmer dedicated to microcontro llers with on-chip flash memory. when using this as on-chip debug emulator, it shou ld be used in combination with a connection cable and a usb interface cable that is used to connect the host machine. target connector specific ations 16-pin general-purpose connector (2.54 mm pitch) remark download the software for operating the qb-mini 2 from the download site for development tools (http://www.necel.com/micro/en/ods/). appendix a development tools user?s manual u17446ej5v0ud 381 a.5 debugging tools (software) id78k0s-qb note (supporting qb-78k0skx1, qb-mini2) integrated debugger this debugger supports the in-circuit emulator s for the 78k0s/kx1+ microcontrollers. the id78k0s-qb is windows-based software. provided with the debug function supporting c l anguage, source programming, disassemble display, and memory display are possible. it should be used in combination with the device file (df789234). sm+ for 78k0s sm+ for 78k0s/kx1+ note system simulator system simulator is windows-based software. it is used to perform debugging at the c source level or assembler level while simulating the operation of the target system on a host machine. use of system simulator allows the execution of application logical testi ng and performance testing on an independent basis from hardware devel opment, thereby providing higher development efficiency and software quality. system simulator should be used in combination with the device file (df789234). the following two types of system simulators supporting the 78k0s/kx1+ microcontrollers are available. ? sm+ for 78k0s (instruction simulation version) this can only simulate a cpu. it is included in the software package. ? sm+ for 78k0s/kx1+ (instruction + peripheral simulation version) this can simulate a cpu and peripheral hardw are (ports, timers, serial interfaces, etc.). note download the id78k0s-qb from the download site for development tools (http://www.necel.com/micro/en/ods/). user?s manual u17446ej5v0ud 382 appendix b notes on designing target system this chapter shows areas on the target system where component mounting is prohibited and areas where there are component mounting height restricti ons when the qb-78k0skx1 is used. for the package drawings of the target connector, exchange adapter, and emulation probe, see the following website. http://www.necel.com/micro/en/devel opment/asia/iecube/outline_qb.html figure b-1. when using the 78k0s/kx1+ em ulation probe (for 30-pin mc package) 17.0 16.0 center point of target connector : exchange adapter tip area components up to 11 mm high can be mounted. : target connector area 8.1 11.0 : 1pin unit : mm top view 17.0 16.0 center point of target connector : exchange adapter tip area components up to 11 mm high can be mounted. : target connector area 8.1 11.0 : 1pin unit : mm top view overview viewing direction ep ea tc iecube overview viewing direction ep ea tc iecube note ep: emulation probe ea: exchange adapter tc: target connector appendix b notes on target system design user?s manual u17446ej5v0ud 383 figure b-2. when using the 78k0s /kx1+ target cable (single track) : a interval pin header more than 2.54mm unit : mm : a contact area of a pin header 0.635 0.635mm (height: 6mm) top view 2.54 2.54 : a interval pin header more than 2.54mm unit : mm : a contact area of a pin header 0.635 0.635mm (height: 6mm) top view 2.54 2.54 overview viewing direction target cable pin header iecube user?s manual u17446ej5v0ud 384 appendix c register index c.1 register index (register name) 8-bit a/d conversion result register (adcrh) ? 171 8-bit compare register 80 (cr80) ? 131 8-bit timer counter 80 (tm80) ? 131 8-bit timer h compare register 01 (cmp01) ? 138 8-bit timer h compare register 11 (cmp11) ? 138 8-bit timer h mode register 1 (tmhmd1) ? 139 8-bit timer mode control register 80 (tmc80) ? 132 10-bit a/d conversion result register (adcr) ? 170 16-bit timer capture/compare register 000 (cr000) ? 90 16-bit timer capture/compare register 010 (cr010) ? 92 16-bit timer counter 00 (tm00) ? 90 16-bit timer mode control register 00 (tmc00) ? 93 16-bit timer output control register 00 (toc00) ? 96 16-bit multiplication result st orage register 0 (mul0) ? 220 [a] a/d converter mode register (adm) ? 168 analog input channel specification register (ads) ? 170 asynchronous serial interface control register 6 (asicl6) ? 195 asynchronous serial interface operation mode register 6 (asim6) ? 189 asynchronous serial interface reception error status register 6 (asis6) ? 191 asynchronous serial interface transmissi on status register 6 (asif6) ? 192 [b] baud rate generator control register 6 (brgc6) ? 194 [c] capture/compare control register 00 (crc00) ? 95 clock selection register 6 (cksr6) ? 193 [e] external interrupt mode register 0 (intm0) ? 231 external interrupt mode register 1 (intm1) ? 232 [f] flash address pointer h (flaph) ? 290 flash address pointer l (flapl) ? 290 flash address pointer h compare register (flaphc) ? 290 flash address pointer l compare register (flaplc) ? 290 flash programming command register (flcmd) ? 289 flash programming mode control register (flpmc) ? 286 flash protect command register (pfcmd) ? 287 flash status register (pfs) ? 287 appendix c register index user?s manual u17446ej5v0ud 385 flash write buffer register (flw) ? 291 [i] input switch control register (isc) ? 197 interrupt mask flag register 0 (mk0) ? 230 interrupt mask flag register 1 (mk1) ? 230 interrupt request flag register 0 (if0) ? 229 interrupt request flag register 1 (if1) ? 229 [l] low-voltage detect register (lvim) ? 261 low-voltage detection level select register (lvis) ? 262 low-speed internal oscillation mode register (lsrcm) ? 76 [m] multiplication data register a (mra0) ? 220 multiplication data register b (mrb0) ? 220 multiplier control register 0 (mulc0) ? 222 [o] oscillation stabilization time se lect register (osts) ? 77, 240 [p] port mode control register 2 (pmc2) ? 69, 171 port mode register 0 (pm0) ? 67 port mode register 2 (pm2) ? 67, 171 port mode register 3 (pm3) ? 67, 98 port mode register 4 (pm4) ? 67, 141, 197 port mode register 12 (pm12) ? 67 port register 0 (p0) ? 68 port register 2 (p2) ? 68 port register 3 (p3) ? 68 port register 4 (p4) ? 68 port register 12 (p12) ? 68 port register 13 (p13) ? 68 preprocessor clock control register (ppcc) ? 75 prescaler mode register 00 (prm00) ? 97 processor clock control register (pcc) ? 75 pull-up resistor option register 0 (pu0) ? 70 pull-up resistor option register 2 (pu2) ? 70 pull-up resistor option register 3 (pu3) ? 70 pull-up resistor option register 4 (pu4) ? 70 pull-up resistor option register 12 (pu12) ? 70 [r] receive buffer register 6 (rxb6) ? 188 receive shift register 6 (rxs6) ? 188 reset control flag register (resf) ? 255 appendix c register index user?s manual u17446ej5v0ud 386 [t] transmit buffer register 6 (txb6) ? 188 transmit shift register 6 (txs6) ? 188 [w] watchdog timer enable register (wdte) ? 155 watchdog timer mode register (wdtm) ? 154 appendix c register index user?s manual u17446ej5v0ud 387 c.2 register index (symbol) [a] adcr: 10-bit a/d conversion result register ? 170 adcrh: 8-bit a/d conversion result register ? 171 adm: a/d converter mode register ? 168 ads: analog input channel specification register ? 170 asicl6: asynchronous serial interface control register 6 ? 195 asif6: asynchronous serial interface transmission status register 6 ? 192 asim6: asynchronous serial interface operation mode register 6 ? 189 asis6: asynchronous serial interface re ception error status register 6 ? 191 [b] brgc6: baud rate generator control register 6 ? 194 [c] cksr6: clock selection register 6 ? 193 cmp01: 8-bit timer h compare register 01 ? 138 cmp11: 8-bit timer h compare register 11 ? 138 cr000: 16-bit timer capture/compare register 000 ? 90 cr010: 16-bit timer capture/compare register 010 ? 92 cr80: 8-bit compare register 80 ? 131 crc00: capture/compare c ontrol register 00 ? 95 [f] flaph: flash address pointer h ? 290 flaphc: flash address pointer h compare register ? 290 flapl: flash address pointer l ? 290 flaplc: flash address pointer l compare register ? 290 flcmd: flash programming command register ? 289 flpmc: flash programming mode control register ? 286 flw: flash write buffer register ? 291 [i] if0: interrupt request flag register 0 ? 229 if1: interrupt request flag register 1 ? 229 intm0: external interrupt mode register 0 ? 231 intm1: external interrupt mode register 1 ? 232 isc: input switch control register ? 197 [l] lsrcm: low-speed internal oscillation mode register ? 76 lvim: low-voltage detect register ? 261 lvis: low-voltage detection level select register ? 262 appendix c register index user?s manual u17446ej5v0ud 388 [m] mk0: interrupt mask flag register 0 ? 230 mk1: interrupt mask flag register 1 ? 230 mra0: multiplication data register a ? 220 mrb0: multiplication data register b ? 220 mul0: 16-bit multiplication re sult storage register 0 ? 220 mulc0: multiplier control register 0 ? 222 [o] osts: oscillation stabilization time select register ? 77, 240 [p] p0: port register 0 ? 68 p2: port register 2 ? 68 p3: port register 3 ? 68 p4: port register 4 ? 68 p12: port register 12 ? 68 p13: port register 13 ? 68 pcc: processor clock control register ? 75 pfcmd: flash protect command register ? 287 pfs: flash status register ? 287 pm0: port mode register 0 ? 67 pm2: port mode register 2 ? 67, 171 pm3: port mode register 3 ? 67, 98 pm4: port mode register 4 ? 67, 141, 197 pm12: port mode register 12 ? 67 pmc2: port mode control register 2 ? 69, 171 ppcc: preprocessor clock control register ? 75 prm00: prescaler mode register 00 ? 97 pu0: pull-up resistor option register 0 ? 70 pu2: pull-up resistor option register 2 ? 70 pu3: pull-up resistor option register 3 ? 70 pu4: pull-up resistor option register 4 ? 70 pu12: pull-up resistor option register 12 ? 70 [r] resf: reset control flag register ? 255 rxb6: receive buffer register 6 ? 188 rxs6: receive shift register 6 ? 188 [t] tm00: 16-bit timer counter 00 ? 90 tm80: 8-bit timer counter 80 ? 131 tmc00: 16-bit timer mode control register 00 ? 93 tmc80: 8-bit timer mode control register 80 ? 132 tmhmd1: 8-bit timer h mode register 1 ? 139 toc00: 16-bit timer output control register 00 ? 96 appendix c register index user?s manual u17446ej5v0ud 389 txb6: transmit buffer register 6 ? 188 txs6: transmit shift register 6 ? 188 [w] wdte: watchdog timer enable register ? 155 wdtm: watchdog timer mode register ? 154 user?s manual u17446ej5v0ud 390 appendix d list of cautions this appendix lists cautions described in this document. ?classification (hard/soft)? in table is as follows. hard: cautions for microcontroller internal/external hardware soft: cautions for software such as register settings or programs (1/20) chapter classification function details of function cautions page chapter 1 hard pin configu- ration av ss pin connect the av ss pin to v ss . p.16 pp. chapter 2 hard pin functions p121/x1 and p122/x2 pins the p121/x1 and p122/x2 pins are pulled down during reset. 21, 22, 24, 25 hard vector table address no interrupt sources correspond to the vector table address 0014h. p.30 since generation of reset si gnal makes the sp contents undefined, be sure to initialize the sp before using the stack memory. p.34 chapter 3 soft memory space sp: stack pointer stack pointers can be set only to the high-speed ram area, and only the lower 10 bits can be actually set. thus, if the stack pointer is specified to 0ff00h, it is converted to 0fb00h in the high-speed ram area, since 0ff00h is in the sfr area and not in the high-speed ram area. when the value is actually pushed onto the stack, 1 is subtracted from 0fb00h to become 0faffh, but since that value is not in the high-speed ram area, it is converted to 0feffh , which is the same value as when 0ff00h is set to the stack pointer. p.34 p121/x1 and p122/x2 pins the p121/x1 and p122/x2 pins are pulled down during reset. p.53 p34 pin because the p34 pin functions alternately as the reset pin, if it is used as an input port pin, the function to input an external reset signal to the reset pin cannot be used. the function of the port is selected by the option byte. for details, refer to chapter 18 option byte. also, since the option byte is referenced af ter the reset release, if low level is input to the reset pin before the referencing, then the reset state is not released. when it is used as an input port pin, connect the pull-up resistor. p.59 p30, p31, and p43 pins because p30, p31, and p43 are also used as external interrupt pins, the corresponding interrupt request flag is set if each of these pins is set to the output mode and its output level is changed. to use the port pin in the output mode, therefore, set the corresponding interrupt mask flag to 1 in advance. p.67 pmc: port mode control register 2 when pmc20 to pmc23 are set to 1, the p20/ani0 to p23/ani3 pins cannot be used as port pins. moreover, be sure to set the pull-up resistor option registers (pu20 to pu23) to 0 for the pins set to a/d converter mode. p.69 chapter 4 hard port functions ? although a 1-bit memory manipulation in struction manipulates 1 bit, it accesses a port in 8-bit units. therefor e, the contents of the output latch of a pin in the input mode, even if it is not subject to manipulation by the instruction, are undefined in a port wi th a mixture of inputs and outputs. p.71 appendix d list of cautions user?s manual u17446ej5v0ud 391 (2/20) chapter classification function details of function cautions page to set and then release the stop mode, set the oscillation stabilization time as follows. expected oscillation stabilization time of resonator oscillation stabilization time set by osts p.77 the wait time after the stop mode is released does not include the time from the release of the stop mo de to the start of clock oscillation (?a? in the figure below), regardless of whether stop mode was released by reset signal generation or interrupt generation. p.77 soft main clock osts: oscillation stabilization time select register the oscillation stabilization time that elapses on power application or after release of reset is selected by the option byte. for details, refer to chapter 18 option byte. p.77 chapter 5 hard crystal/ ceramic oscillator ? when using the crystal/ceramic oscillator, wire as follows in the area enclosed by the broken lines in figure 5-6 to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. p.78 pp. even if tm00 is read, the value is not captured by cr010. 90, 122 pp. hard tm00: 16-bit timer counter 00 when tm00 is read, count misses do not occur, since the input of the count clock is temporarily stopped and then resumed after the read. 90, 122 pp. set cr000 to other than 0000h in the clear & start mode entered on match between tm00 and cr000. this means a 1-pulse count operation cannot be performed when this register is us ed as an external event counter. 91, 122 pp. in the free-running mode and in the clear & start mode using the valid edge of ti000 pin, if cr000 is set to 0000h, an interrupt request (inttm000) is generated when cr000 changes from 0000h to 0001h following overflow (ffffh). 91, 122 pp. if the new value of cr000 is less than the value of 16-bit timer counter 0 (tm00), tm00 continues counting, overfl ows, and then starts counting from 0 again. if the new value of cr000 is less than the old value, therefore, the timer must be reset to be restarted after the value of cr000 is changed. 91, 122 pp. soft the value of cr000 after 16-bit timer/event counter 00 has stopped is not guaranteed. 91, 123 pp. the capture operation may not be performed for cr000 set in compare mode even if a capture trigger is input. 91, 126 pp. chapter 6 hard 16-bit timer/event counter 00 cr000: 16-bit timer capture/ compare register 000 when using p31 as the input pin (ti010) of the valid edge, it cannot be used as a timer output pin (to00). when us ing p31 as the timer output pin (to00), it cannot be used as the input pin (ti010) of the valid edge. 91, 127 appendix d list of cautions user?s manual u17446ej5v0ud 392 (3/20) chapter classification function details of function cautions page pp. hard if the register read period and the input of the capture trigger conflict when cr000 is used as a capture register, the capture trigger input takes precedence and the read data is undefined. also, if the count stop of the timer and the input of the capture trigger conf lict, the capture trigger is undefined. 91, 125 cr000: 16-bit timer capture/ compare register 000 changing the cr000 setting during tm00 operation may cause a malfunction. to change the setting, refer to 6.5 cautions related to 16-bit timer/event counter 00 (17) changing compare register during timer operation. p.92 pp. in the free-running mode and in the clear & start mode using the valid edge of the ti000 pin, if cr010 is set to 0000h, an interrupt request (inttm010) is generated when cr010 changes from 0000h to 0001h following overflow (ffffh). 92, 122 pp. if the new value of cr010 is less than the value of 16-bit timer counter 0 (tm00), tm00 continues counting, overfl ows, and then starts counting from 0 again. if the new value of cr010 is less than the old value, therefore, the timer must be reset to be restarted after the value of cr010 is changed. 92, 122 pp. soft the value of cr010 after 16-bit timer/event counter 00 has stopped is not guaranteed. 92, 123 pp. the capture operation may not be performed for cr010 set in compare mode even if a capture trigger is input. 92, 126 pp. hard if the register read period and the input of the capture trigger conflict when cr010 is used as a capture register, the capture trigger input takes precedence and the read data is undefined. also, if the timer count stop and the input of the capture trigger conflict, the capture data is undefined. 93, 125 cr010: 16-bit timer capture/ compare register 010 changing the cr010 setting during tm00 operation may cause a malfunction. to change the setting, refer to 6.5 cautions related to 16-bit timer/event counter 00 (17) changing compare register during timer operation. p.93 pp. 16-bit timer counter 00 (tm00) starts operation at the moment tmc002 and tmc003 (operation stop mode) are set to a value other than 0, 0, respectively. set tmc002 and tmc003 to 0, 0 to stop the operation. 93, 122 pp. soft the timer operation must be stopped before writing to bits other than the ovf00 flag. 94, 123 pp. hard if the timer is stopped, timer counts and timer interrupts do not occur, even if a signal is input to the ti000/ti010 pins. 94, 122 pp. except when the valid edge of the ti000 pin is selected as the count clock, stop the timer operation before setti ng stop mode or system clock stop mode; otherwise the timer may malfunc tion when the system clock starts. 94, 127 pp. set the valid edge of the ti000 pin with bits 4 and 5 of prescaler mode register 00 (prm00) after stopping the timer operation. 94, 123 if the clear & start mode entered on a match between tm00 and cr000, clear & start mode at the valid edge of the ti000 pin, or free-running mode is selected, when the set value of cr000 is ffffh and the tm00 value changes from ffffh to 0000h, the ovf00 flag is set to 1. p.94 pp. chapter 6 soft 16-bit timer/event counter 00 tmc00: 16-bit timer mode control register 00 even if the ovf00 flag is cleared befor e the next count clock is counted (before tm00 becomes 0001h) after the occurrence of a tm00 overflow, the ovf00 flag is re-set newly and clear is disabled. 94, 124 appendix d list of cautions user?s manual u17446ej5v0ud 393 (4/20) chapter classification function details of function cautions page pp. tmc00: 16-bit timer mode control register 00 the capture operation is performed at the fall of the count clock. an interrupt request input (inttm0n0), however, occurs at the rise of the next count clock. 94, 125 pp. the timer operation must be stopped before setting crc00. 95, 123 pp. soft when the clear & start mode entered on a match between tm00 and cr000 is selected by 16-bit timer mode control register 00 (tmc00), cr000 should not be specified as a capture register. 95, 122 pp. hard crc00: capture /compare control register 00 to ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two cycles of the c ount clock selected by prescaler mode register 00 (prm00) (refer to figure 6-17). 95, 125 pp. the timer operation must be stopped before setting other than ospt00. 96, 123 pp. if lvs00 and lvr00 are read, 0 is read. 96, 123 pp. ospt00 is automatically cleared a fter data is set, so 0 is read. 96, 123 pp. soft do not set ospt00 to 1 other than in one-shot pulse output mode. 96, 123 pp. hard a write interval of two cycles or more of the count clock selected by prescaler mode register 00 (prm00) is required, when ospt00 is set to 1 successively. 96, 123 toc00: 16-bit timer output control register 00 when toe00 is 0, set toe00, lvs00, and lvr00 at the same time with the 8-bit memory manipulation instruction. when toe00 is 1, lvs00 and lvr00 can be set with the 1-bit memo ry manipulation instruction. p.96 pp. always set data to prm00 after stopping the timer operation. 98, 123 pp. soft if the valid edge of the ti000 pin is to be set as the count clock, do not set the clear/start mode and the capture trigger at the valid edge of the ti000 pin. 98, 125 pp. chapter 6 hard 16-bit timer/event counter 00 prm00: prescaler mode register 00 in the following cases, note with caution that the valid edge of the ti0n0 pin is detected. <1> immediately after a system reset, if a high level is input to the ti0n0 pin, the operation of the 16-bit timer counter 00 (tm00) is enabled if the rising edge or both rising an d falling edges are specified as the valid edge of the ti0n0 pin, a rising edge is detected immediately after the tm00 operation is enabled. <2> if the tm00 operation is stopped while the ti0n0 pin is high level, tm00 operation is then enabled after a low level is input to the ti0n0 pin if the falling edge or both rising and falling edges are specified as the valid edge of the ti0n0 pin, a falling edge is detected immediately after the tm00 operation is enabled. <3> if the tm00 operation is stopped while the ti0n0 pin is low level, tm00 operation is then enabled after a high level is input to the ti0n0 pin if the rising edge or both rising an d falling edges are specified as the valid edge of the ti0n0 pin, a rising edge is detected immediately after the tm00 operation is enabled. 98, 127 appendix d list of cautions user?s manual u17446ej5v0ud 394 (5/20) chapter classification function details of function cautions page pp. the sampling clock used to eliminate noise differs when a ti000 valid edge is used as the count clock and when it is us ed as a capture trigger. in the former case, the count clock is f xp , and in the latter case the count clock is selected by prescaler mode register 00 (prm 00). the capture operation is not performed until the valid edge is sampled and the valid level is detected twice, thus eliminating noise wi th a short pulse width. 98, 127 pp. hard prm00: prescaler mode register 00 when using p31 as the input pin (ti010) of the valid edge, it cannot be used as a timer output pin (to00). when us ing p31 as the timer output pin (to00), it cannot be used as the input pin (ti010) of the valid edge. 98, 127 interval timer changing the cr000 setting during tm00 operation may cause a malfunction. to change the setting, refer to 6.5 cautions related to 16-bit timer/event counter 00 (17) changing compare register during timer operation. p.99 pp. external event counter when reading the external event counter count value, tm00 should be read. 103, 127 pp. to use two capture registers, set the ti000 and ti010 pins. 104, 125 pp. pulse width measurement the measurable pulse width in this operation example is up to 1 cycle of the timer counter. 105, 107, 108, 110 square-wave output changing the cr000 setting during tm00 operation may cause a malfunction. to change the setting, refer to 6.5 cautions related to 16-bit timer/event counter 00 (17) changing compare register during timer operation. p.112 changing the crc0n0 setting during tm00 operation may cause a malfunction. to change the setting, refer to 6.5 cautions related to 16-bit timer/event counter 00 (17) changi ng compare register during timer operation. p.114 pp. values in the following range should be set in cr000 and cr010. 0000h < cr010 < cr000 ffffh 115, 127 pp. ppg output the cycle of the pulse generated through ppg output (cr000 setting value + 1) has a duty of (cr010 setting va lue + 1)/(cr000 setting value + 1). 115, 127 pp. soft do not set the ospt00 bit to 1 again while the one-shot pulse is being output. to output the one-shot pulse again, wait until the current one-shot pulse output is completed. 117, 123 pp. hard when using the one-shot pulse output of 16-bit timer/event counter 00 with a software trigger, do not change the level of the ti000 pin or its alternate- function port pin. because the external trigger is valid ev en in this case, the timer is cleared and started even at the level of the ti000 pin or its alternate-function port pin, resulting in the output of a pulse at an undesired timing. 117, 123 pp. do not set 0000h to the cr000 and cr010 registers. 118, 123 pp. chapter 6 soft 16-bit timer/event counter 00 one-shot pulse output by software 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop mode) is set to the tmc003 and tmc002 bits. 119, 122 appendix d list of cautions user?s manual u17446ej5v0ud 395 (6/20) chapter classification function details of function cautions page pp. hard do not input the external trigger a gain while the one-shot pulse is being output. to output the one-shot pulse again, wait until the current one-shot pulse output is completed. 119, 124 pp. do not set 0000h to the cr000 and cr010 registers. 120, 124 pp. soft one-shot pulse output with external trigger 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop mode) is set to the tmc003 and tmc002 bits. 121, 122 hard timer start errors an error of up to one clock may occur in the time required for a match signal to be generated after timer start. this is because 16-bit timer counter 00 (tm00) is started asynchronously to the count clock. p.122 one-shot pulse output one-shot pulse output normally operate s only in the free-running mode or in the clear & start mode at the valid edge of the ti000 pin. because an overflow does not occur in the clear & start mode on a match between tm00 and cr000, one-shot pulse output is not possible. p.123 if both the rising and falling edges are selected as the valid edges of the ti000 pin, capture is not performed. p.125 capture operation when the crc001 bit value is 1, the tm00 count value is not captured in the cr000 register when a valid edge of the ti010 pin is detected, but the input from the ti010 pin can be used as an external interrupt source because inttm000 is generated at that timing. p.125 with the 16-bit timer capture/compare register 0n0 (cr0n0) used as a compare register, when changing cr0n0 around the timing of a match between 16-bit timer counter 00 (tm00) and 16-bit timer capture/compare register 0n0 (cr0n0) during timer counting, the change timing may conflict with the timing of the match, so the operation is not guaranteed in such cases. to change cr0n0 during timer counting, follow the procedure below using an inttm000 interrupt. p.126 changing compare register during timer operation if cr010 is changed during timer counti ng without performing processing <1> above, the value in cr010 may be rewritten twice or more, causing an inversion of the output level of the to00 pin at each rewrite. p.126 soft external event counter the timing of the count start is after two valid edge detections. p.127 when using an input pulse of the ti000 pin as a count clock (external trigger), be sure to input the pulse width which sati sfies the ac characteristics. for the ac characteristics, refer to chapter 22 and chapter 23 electrical specifications. p.128 chapter 6 hard 16-bit timer/event counter 00 external clock limitation when an external waveform is input to 16-bit timer/event counter 00, it is sampled by the noise limiter circuit and thus an error occurs on the timing to become valid inside the device. p.128 cr80: 8-bit compare register 80 when changing the value of cr80, be sure to stop the timer operation. if the value of cr80 is changed with the timer operation enabled, a match interrupt request signal is generated immediat ely and the timer may be cleared. p.131 be sure to set tmc80 after stopping the timer operation. p.132 chapter 7 soft 8-bit timer 80 tmc80: 8-bit timer mode control register 80 be sure to clear bits 0 and 6 to 0. p.132 appendix d list of cautions user?s manual u17446ej5v0ud 396 (7/20) chapter classification function details of function cautions page when changing the value of cr80, be sure to stop the timer operation. if the value of cr80 is changed with the timer operation enabled, a match interrupt request signal may be generated immediately. p.133 soft interval timer if the count clock of tmc80 is set and the operation of tm80 is enabled at the same time by using an 8-bit memory mani pulation instruction, the error of one cycle after the timer is started may be 1 clock or more. therefore, be sure to follow the above sequence when using tm80 as an interval timer. p.133 hard error when timer starts the time from starting the timer to generation of the match signal includes an error of up to 1.5 clocks. this is because, if the timer is started while the count clock is high, the rising edge may be immediately detected and the counter may be incremented (refer to figure 7-6). p.135 cr80: 8-bit compare register 80 8-bit compare register 80 (cr80) can be set to 00h. p.135 chapter 7 soft 8-bit timer 80 stop mode before executing the stop instruction, be sure to stop the timer operation (tce80 = 0). p.135 cmp01: 8-bit timer h compare register 01 cmp01 cannot be rewritten during timer count operation. p.138 cmp11: 8-bit timer h compare register 11 in the pwm output mode, be sure to set cmp11 when starting the timer count operation (tmhe1 = 1) after the timer count operation was stopped (tmhe1 = 0) (be sure to set again even if setting the same value to cmp11). p.138 when tmhe1 = 1, setting the other bits of the tmhmd1 register is prohibited. p.140 soft tmhmd1: 8-bit timer h mode register 1 in the pwm output mode, be sure to set 8-bit timer h compare register 11 (cmp11) when starting the timer count operation (tmhe1 = 1) after the timer count operation was stopped (tmhe1 = 0) (be sure to set again even if setting the same value to the cmp11 register). p.140 hard in pwm output mode, the setting value for the cmp11 register can be changed during timer count operation. however, three operation clocks (signal selected using the cks12 to cks 10 bits of the tmhmd1 register) or more are required to transfer the regi ster value after rewriting the cmp11 register value. p.146 be sure to set the cmp11 register when starting the timer count operation (tmhe1 = 1) after the timer count operation was stopped (tmhe1 = 0) (be sure to set again even if setting the sa me value to the cmp11 register). p.146 chapter 8 soft 8-bit timer h1 pwm output make sure that the cmp11 register setting value (m) and cmp01 register setting value (n) are within the following range. 00h cmp11 (m) < cmp01 (n) ffh p.147 set bits 7, 6, and 5 to 0, 1, and 1, respectively. do not set the other values. p.155 chapter 9 soft watchdog timer wdtm: watchdog timer mode register after reset is released, wdtm can be written only once by an 8-bit memory manipulation instruction. if writing is attempted a second time, an internal reset signal is generated. however, at t he first write, if ?1? and ?x? are set for wdcs4 and wdcs3 respectively and the watchdog timer is stopped, then the internal reset signal does not occur even if the following are executed. ? second write to wdtm ? 1-bit memory manipulation instruction to wdte ? writing of a value other than ?ach? to wdte p.155 appendix d list of cautions user?s manual u17446ej5v0ud 397 (8/20) chapter classification function details of function cautions page wdtm cannot be set by a 1-bit memo ry manipulation instruction. p.155 wdtm: watchdog timer mode register when using the flash memory progra mming by self programming, set the overflow time for the watchdog timer so that enough overflow time is secured (example 1-byte writing: 200 s min., 1-block deletion: 10 ms min.). p.155 if a value other than ach is written to wdte, an internal reset signal is generated. p.155 if a 1-bit memory manipulation instructi on is executed for wdte, an internal reset signal is generated. p.155 soft wdte: watchdog timer enable register the value read from wdte is 9ah (this di ffers from the written value (ach)). p.155 when ?low-speed internal oscillator cannot be stopped? is selected by option byte in this mode, operation of the watchdog timer cannot be stopped even during stop instruction execution. for 8-bit timer h1 (tmh1), a division of the low- speed internal oscillation clock can be selected as the count source, so clear the watchdog timer using the interrupt request of tmh1 before the watchdog timer overflows after stop instruction ex ecution. if this processing is not performed, an internal reset signal is generated when the watchdog timer overflows after stop instruction execution. p.156 chapter 9 hard watchdog timer when ?low-speed internal oscillator can be stopped by software? is selected by option byte in this mode, watchdog timer operation is stopped during halt/stop instruction execution. after halt/stop mode is released, counting is started again using the operation clock of the watchdog timer set before halt/stop instruction execution by wdtm. at this time, the counter is not cleared to 0 but holds its value. p.158 sampling time and conversion time the above sampling time and conver sion time do not include the clock frequency error. select the sampling time and conversion time such that notes 2 and 3 above are satisfied, while taking the clock frequency error into consideration (an error margin maximum of 5% when using the high-speed internal oscillator). p.164 the above sampling time and conver sion time do not include the clock frequency error. select the sampling time and conversion time such that notes 3 and 4 above are satisfied, while taking the clock frequency error into consideration (an error margin maximum of 5% when using the high-speed internal oscillator). p.169 if a bit other than adcs of adm is manipulated while a/d conversion is stopped (adcs = 0) and then a/d conversion is started, execute two nop instructions or an instruction equival ent to two machine cycles, and set adcs to 1. p.170 a/d conversion must be stopped (adcs = 0) be fore rewriting bits fr0 to fr2. p.170 adm: a/d converter mode register be sure to clear bits 6, 2, and 1 to 0. p.170 ads: analog input channel specification register be sure to clear bits 2 to 7 of ads to 0. p.170 chapter 10 soft a/d converter adcr: 10-bit a/d conversion result register when writing to the a/d converter mode register (adm) and analog input channel specification register (ads), the contents of adcr may become undefined. read the conversion result following conversion completion before writing to adm and ads. using timing other than the above may cause an incorrect conversion result to be read. p.170 appendix d list of cautions user?s manual u17446ej5v0ud 398 (9/20) chapter classification function details of function cautions page pmc2: port mode control register 2 when pmc20 to pmc23 are set to 1, the p20/ani0 to p23/ani3 pins cannot be used as port pins. be sure to set the pull-up resistor option registers (pu20 to pu23) to 0 for the pins set to a/d converter mode. p.171 pp. make sure the period of <1> to <4> is 1 s or more. 172, 176 pp. it is no problem if the order of <1> and <2> is reversed. 172, 176 <1> can be omitted. however, ignore the data resulting from the first conversion after <4> in this case. p.176 soft a/d converter operations the period from <5> to <8> differs from the conversion time set using bits 5 to 3 (fr2 to fr0) of adm. the period from <7> to <8> is the conversion time set using fr2 to fr0. p.176 operating current in stop mode to satisfy the dc characte ristics of the supply current in the stop mode, clear bit 7 (adcs) and bit 0 (adce) of the a/d converter mode register (adm) to 0 before executing the stop instruction. p.179 hard input range of ani0 to ani3 observe the rated range of the ani0 to ani3 input voltage. if a voltage of av ref or higher and av ss or lower (even in the range of absolute maximum ratings) is input to an analog input c hannel, the converted value of that channel becomes undefined. in addition, the converted values of the other channels may also be affected. p.179 adcr, adcrh read has priority. after the read operation, the new conversion result is written to adcr, adcrh. p.179 soft conflicting operations adm or ads write has priority. adcr, adcrh write is not performed, nor is the conversion end interrupt signal (intad) generated. p.179 noise countermeasures to maintain the 10-bit resolution, attention must be paid to noise input to the av ref pin and pins ani0 to ani3. <1> connect a capacitor with a low equivalent resistance and a high frequency response to the power supply. <2> because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally, as shown in figure 10-19, to reduce noise. <3> do not switch the a/d conversion function of the ani0 to ani3 pins to their alternate functi ons during conversion. <4> the conversion accuracy can be improved by setting halt mode immediately after the conversion starts. p.179 the analog input pins (ani0 to ani3) are al so used as input port pins (p20 to p23). when a/d conversion is performed with any of ani0 to ani3 selected, do not access port 2 (p20 to p23) while conv ersion is in progress; otherwise the conversion resolution may be degraded. p.180 chapter 10 hard a/d converter ani0/p20 to ani3/p23 if a digital pulse is applied to the pins adjacent to the pins currently used for a/d conversion, the expected value of the a/d conversion may not be obtained due to coupling noise. therefor e, do not apply a pulse to the pins adjacent to the pin undergoing a/d conversion. p.180 appendix d list of cautions user?s manual u17446ej5v0ud 399 (10/20) chapter classification function details of function cautions page hard input impedance of ani0 to ani3 pins in this a/d converter, the internal sampling capacitor is charged and sampling is performed during sampling time. since only the leakage current flows other than during sampling and the current for charging the capacitor also flows during sampling, the input impedance fluctuates both during sampling and otherwise. if the shortest conversion time of the reference voltage is used, to perform sufficient sampling, it is recommended to make the output impedance of the analog input source 1 k or lower, or attach a capacitor of around 0.01 f to 0.1 f to the ani0 to ani3 pins (see figure 10-19). p.180 adif: interrupt request flag the interrupt request flag (adif) is not cleared even if the analog input channel specification regi ster (ads) is changed. therefore, if an analog input pin is changed during a/d conversion, the a/d conversion result and adif for the pr e-change analog input may be set just before the ads rewrite. caution is ther efore required since, at this time, when adif is read immediately after the ads rewrite, adif is set despite the fact a/d conversion for the post-change analog input has not ended. when a/d conversion is stopped and then resumed, clear adif before the a/d conversion operation is resumed. p.180 conversion results just after a/d conversion start the first a/d conversion value immediat ely after a/d conversion starts may not fall within the rating range if the adcs bit is set to 1 within 1 s after the adce bit was set to 1, or if the adcs bi t is set to 1 with the adce bit = 0. take measures such as polling the a/d conversion end interrupt request (intad) and removing the fi rst conversion result. p.181 soft a/d conversion result register (adcr, adcrh) read operation when a write operation is performed to the a/d converter mode register (adm) and analog input channel specificat ion register (ads), the contents of adcr and adcrh may become undefined. read the conversion result following conversion completion before writing to adm and ads. using a timing other than the above may cause an incorrect conversion result to be read. p.181 chapter 10 hard a/d converter operating current at conversion waiting mode the dc characteristic of the operating current during the stop mode is not satisfied due to the conversion waiti ng mode (only the comparator consumes power), when bit 7 (adcs) and bit 0 (adce) of the a/d converter mode register (adm) are set to 0 and 1 respectively. p.181 hard the t x d6 output inversion function invert s only the transmission side and not the reception side. to use this functi on, the reception side must be ready for reception of inverted data. p.182 if clock supply to se rial interface uart6 is not stopped (e.g., in the halt mode), normal operation continues. if clock supply to seri al interface uart6 is stopped (e.g., in the stop mode), each register stops operating, and holds the value immediately befor e clock supply was stopped. the txd6 pin also holds the value immediat ely before clock supply was stopped and outputs it. however, the operation is not guaranteed after clock supply is resumed. therefore, reset the circuit so that power6 = 0, rxe6 = 0, and txe6 = 0. p.182 chapter 11 soft serial interface uart6 uart mode if data is continuously transmitted, the communication timing from the stop bit to the next start bit is extended two operating clocks of the macro. however, this does not affect the result of communication because the reception side initializes the timing when it has detected a start bit. do not use the continuous transmission function if the interface used in lin communication operation. p.182 appendix d list of cautions user?s manual u17446ej5v0ud 400 (11/20) chapter classification function details of function cautions page rxb6: receive buffer register 6 reception enable status is entered, after having set rxe6 to 1 and one clock of the base clock (f xclk6 ) has elapsed. p.188 when starting transmission, write transmit data to txb6, after having set txe6 to 1 and a wait of one clock or more of the base clock (f xclk6 ) has been performed. p.188 do not write data to txb6 when bit 1 (txbf6) of asynchronous serial interface transmission status register 6 (asif6) is 1. p.188 txb6: transmit buffer register 6 do not refresh (write the same value to) txb6 by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asynchronous serial interface operati on mode register 6 (asim6) are 1 or when bit 7 (power6) and bit 5 (rxe6) of asim6 are 1). when outputting same values in continuous transmission, be sure to confirm that txbf6 is 0 before writing the same values to txb6. p.188 at startup, transmission operation is st arted by setting txe6 to 1 after having set power6 to 1, then setting the transmit data to txb6 after having waited for one clock or more of the base clock (f xclk6 ). when stopping transmission operation, set power6 to 0 after having set txe6 to 0. p.190 at startup, reception enable status is entered after having set power6 to 1, then setting rxe6 to 1, and one clock of the base clock (f xclk6 ) has elapsed. when stopping reception operation, set power6 to 0 after having set rxe6 to 0. p.191 set power6 = 1 rxe6 = 1 in a state where a high level has been input to the rxd6 pin. if power6 = 1 rxe6 = 1 is set during low-level input, reception is started and correct data will not be received. p.191 clear the txe6 and rxe6 bits to 0 before rewriting the ps61, ps60, and cl6 bits. p.191 fix the ps61 and ps60 bits to 0 when the interface is used in lin communication operation. p.191 make sure that txe6 = 0 when rewriting the sl6 bit. reception is always performed with ?the number of stop bits = 1?, and therefore, is not affected by the set value of the sl6 bit. p.191 asim6: asynchronous serial interface operation mode register 6 make sure that rxe6 = 0 when rewriting the isrm6 bit. p.191 the operation of the pe6 bit differs depending on the set values of the ps61 and ps60 bits of asynchronous serial interface operation mode register 6 (asim6). p.191 the first bit of the receive data is ch ecked as the stop bit, regardless of the number of stop bits. p.191 if an overrun error occurs, the next receive data is not written to receive buffer register 6 (rxb6) but discarded. p.191 pp. chapter 11 soft serial interface uart6 asis6: asynchronous serial interface reception error status register 6 be sure to read asis6 before reading receive buffer register 6 (rxb6). 191, 209 appendix d list of cautions user?s manual u17446ej5v0ud 401 (12/20) chapter classification function details of function cautions page to transmit data continuously, write the first transmit data (first byte) to the txb6 register. be sure to check that the txbf6 flag is ?0?. if so, write the next transmit data (second byte) to the t xb6 register. if data is written to the txb6 register while the txbf6 flag is ?1?, the transmit data cannot be guaranteed. p.192 asif6: asynchronous serial interface transmission status register 6 to initialize the transmission unit upon co mpletion of continuous transmission, be sure to check that the txsf6 flag is ?0? after generation of the transmission completion interrupt, and then execute initia lization. if initia lization is executed while the txsf6 flag is ?1?, the transmit data cannot be guaranteed. p.192 cksr6: clock selection register 6 make sure power6 = 0 when rewriting tps63 to tps60. p.193 soft make sure that bit 6 (txe6) and bit 5 (rxe6) of the asim6 register = 0 when rewriting the mdl67 to mdl60 bits. p.194 hard brgc6: baud rate generator control register 6 the baud rate is the output clock of the 8-bit counter divided by 2. p.194 asicl6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 are 1 or when bit 7 (power6) and bit 5 (rxe6) of asim6 are 1), if 0 data has been written to asicl6 by sbrt6 and sbtt6. p.195 in the case of an sbf reception error, return to sbf reception mode again. the status of the sbrf6 flag will be held (1). for details on sbf reception refer to (2) ? (i) sbf reception in 11.4.2 asynchronous serial interface (uart) mode described later. p.196 before setting the sbrt6 bit to 1, make sure that bit 7 (power6) and bit 5 (rxe6) of asim6 = 1. moreover, after setting the sbrt6 bit to 1, do not clear the sbrt6 bit to 0 before the sbf reception ends (an interrupt request signal is generated). p.196 the read value of the sbrt6 bit is always 0. sbrt6 is automatically cleared to 0 after sbf reception has been correctly completed. p.196 before setting the sbtt6 bit to 1, make sure that bit 7 (power6) and bit 6 (txe6) of asim6 = 1. moreover, after setting the sbtt6 bit to 1, do not clear the sbtt6 bit to 0 before the sbf transmission ends (an interrupt request signal is generated). p.196 the read value of the sbtt6 bit is alwa ys 0. sbtt6 is automatically cleared to 0 at the end of sbf transmission. p.196 asicl6: asynchronous serial interface control register 6 before rewriting the dir6 and txdlv6 bits, clear the txe6 and rxe6 bits to 0. p.196 chapter 11 soft serial interface uart6 bits 7, 6, and 5 (power6, txe6, and rxe6) of asim6 clear power6 to 0 after clearing txe6 and rxe6 to 0 to set the operation stop mode. to start the operation, set power6 to 1, and then set txe6 and rxe6 to 1. p.198 appendix d list of cautions user?s manual u17446ej5v0ud 402 (13/20) chapter classification function details of function cautions page uart mode take the relationship with the ot her party of communication into consideration when setting the port mode register and port register. in order to avoid the generation of unintended start bits (falling signals), set pm43 to 0 (output) after having set p43 to 1. p.199 parity types and operation fix the ps61 and ps60 bits to 0 when the interface is used in lin communication operation. p.203 use the value of the txbf6 flag to j udge whether continuous transmission is possible. do not write the next tran smit data, by making a judgment only by the fact that the txsf6 flag has been set to 1. p.205 continuous transmission when the interface is used in lin communication operation, the continuous transmission function cannot be used. make sure that asynchronous serial interface transmission status register 6 (asif6) is 00h before writing transmit data to transmit buffer register 6 (txb6). p.205 txbf6 during continuous transmission: bit 1 of asif6 to transmit data continuously, write the first transmit data (first byte) to the txb6 register. be sure to check that the txbf6 flag is ?0?. if so, write the next transmit data (second byte) to the t xb6 register. if data is written to the txb6 register while the txbf6 flag is ?1?, the transmit data cannot be guaranteed. p.205 txsf6 during continuous transmission: bit 0 of asif6 to initialize the transmission unit upon co mpletion of continuous transmission, be sure to check that the txsf6 flag is ?0? after generation of the transmission completion interrupt, and then execute initia lization. if initia lization is executed while the txsf6 flag is ?1?, the transmit data cannot be guaranteed. p.205 be sure to read receive buffer register 6 (rxb6) even if a reception error occurs. otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. p.209 reception is always performed with the ?number of stop bits = 1?. the second stop bit is ignored. p.209 normal reception be sure to read asynchronous serial inte rface reception error status register 6 (asis6) before reading rxb6. p.209 keep the baud rate error during transmission to within the permissible error range at the reception destination. p.215 generation of serial clock make sure that the baud rate error dur ing reception satisfies the range shown in (4) permissible baud rate range during reception. p.215 chapter 11 soft serial interface uart6 permissible baud rate range during reception make sure that the baud rate error duri ng reception is within the permissible error range, by using the calculation expression shown below. p.217 mul0: 16-bit multiplication result storage register 0 although this register is manipulated with a 16-bit memory manipulation instruction, it can be also manipulat ed with an 8-bit memory manipulation instruction. when using an 8-bit memo ry manipulation instruction, however, access the register by means of direct addressing. p.220 chapter 12 soft multiplier mulc0: control register 0 be sure to clear bits 1 to 7 to 0. p.222 appendix d list of cautions user?s manual u17446ej5v0ud 403 (14/20) chapter classification function details of function cautions page hard vector table address no interrupt sources correspond to the vector table address 0014h. p.226 pp. if0, if1: interrupt request flag registers 0, 1 mk0, mk1: interrupt mask flag registers 0, 1 because p30, p31, p41, and p43 have an alternate function as external interrupt inputs, when the output leve l is changed by specifying the output mode of the port function, an interrupt request flag is set. therefore, the interrupt mask flag should be set to 1 before using the output mode. 229, 230 be sure to clear bits 0 and 1 to 0. p.231 intm0: external interrupt mode register 0 before setting the intm0 register, be sure to set the corresponding interrupt mask flag ( mk = 1) to disable interrupts. after setting the intm0 register, clear the interrupt request flag ( if = 0), then clear the interrupt mask flag ( mk = 0), which will enable interrupts. p.231 be sure to clear bits 2 to 7 to 0. p.232 intm1: external interrupt mode register 1 before setting intm1, set pmk3 to 1 to disable interrupts. to enable interrupts, clear pif3 to 0, then clear pmk3 to 0. p.232 interrupt request pending interrupt requests will be held pending while the interrupt request flag registers 0, 1 (if0, if1) or interrupt mask flag registers 0, 1 (mk0, mk1) are being accessed. p.235 chapter 13 soft interrupt function multiple interrupt servicing multiple interrupts can be acknowledged even for low-priority interrupts. p.236 soft ? the lsrstop setting is valid only when ?can be stopped by software? is set for the low-speed internal oscillator by the option byte. p.238 stop mode when shifting to the stop mode, be sure to stop the peripheral hardware operation before executing stop instruction (except the peripheral hardware that operates on the low-speed internal oscillation clock). p.239 stop mode, halt mode the following sequence is recommended for operating current reduction of the a/d converter when the standby function is used: first clear bit 7 (adcs) and bit 0 (adce) of the a/d converter mode register (adm) to 0 to stop the a/d conversion operation, and then execute the halt or stop instruction. p.239 hard stop mode if the low-speed internal oscillator is operating before the stop mode is set, oscillation of the low-speed internal oscillation clock cannot be stopped in the stop mode (refer to table 14-1). p.239 soft to set and then release the stop mode, set the oscillation stabilization time as follows. expected oscillation stabilization time of resonator oscillation stabilization time set by osts p.240 hard the wait time after the stop mode is released does not include the time from the release of the stop mo de to the start of clock oscillation (?a? in the figure below), regardless of whether stop mode was released by reset signal generation or interrupt generation. p.240 chapter 14 soft standby function osts: oscillation stabilization time select register the oscillation stabilization time that elapses on power application or after release of reset is selected by the option byte. for details, refer to chapter 18 option byte. p.240 appendix d list of cautions user?s manual u17446ej5v0ud 404 (15/20) chapter classification function details of function cautions page settings and operating statuses in halt mode because an interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. p.241 chapter 14 soft standby function settings and operating statuses in stop mode because an interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediatel y cleared if set. thus, in the stop mode, the normal operation mode is restored after the stop instruction is executed and then the operation is stopped for 34 s (typ.) (after an additional wait time for stabilizing the oscillation set by the oscillation stabilization time select register (osts) has elapsed when crystal/ceramic oscillation is used). p.244 for an external reset, input a low level for 2 s or more to the reset pin. p.248 during reset signal generation, the s ystem clock and low-speed internal oscillation clock stop oscillating. p.248 when the reset pin is used as an input-only port pin (p34), the 78k0s/kb1+ is reset if a low level is input to the reset pin after reset is released by the poc circuit, the lvi circuit and the wa tchdog timer and before the option byte is referenced again. the reset status is retained until a high level is input to the reset pin. p.248 ? the lvi circuit is not reset by the inter nal reset signal of the lvi circuit. p.249 hard timing of reset by overflow of watchdog timer the watchdog timer is also reset in the case of an internal reset of the watchdog timer. p.251 chapter 15 soft reset function resf: reset control flag register do not read data by a 1-bit memory manipulation instruction. p.255 soft if an internal reset signal is generated in the poc circuit, the reset control flag register (resf) is cleared to 00h. p.256 hard functions of power-on-clear circuit use these products in the following voltage range because the detection voltage (v poc ) of the poc circuit is the supply voltage range. standard product, (a) grade product: 2.2 to 5.5 v, (a2) grade product: 2.26 to 5.5 v p.256 chapter 16 soft power-on- clear circuit cautions for power-on-clear circuit in a system where the supply voltage (v dd ) fluctuates for a certain period in the vicinity of the poc detection voltage (v poc ), the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action. p.258 to stop lvi, follow either of the procedures below. ? when using 8-bit mani pulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0. p.261 lvim: low- voltage detect register be sure to set bits 2 to 6 to 0. p.261 bits 4 to 7 must be set to 0. p.262 chapter 17 soft low- voltage detector lvis: low- voltage detection level select register if values other than same values are written during lvi operation, the value becomes undefined at the very moment it is written, and thus be sure to stop lvi (bit 7 of lvim register (lvion) = 0) before writing. p.262 appendix d list of cautions user?s manual u17446ej5v0ud 405 (16/20) chapter classification function details of function cautions page <1> must always be executed. when lvimk = 0, an interrupt may occur immediately after the processing in <3>. p.263 when used as reset if supply voltage (v dd ) detection voltage (v lvi ) when lvim is set to 1, an internal reset signal is not generated. p.263 chapter 17 soft low- voltage detector cautions for low- voltage detector in a system where the supply voltage (v dd ) fluctuates for a certain period in the vicinity of the lvi detection voltage (v lvi ), the operation is as follows depending on how the low-voltage detector is used. <1> when used as reset the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action (1) below. <2> when used as interrupt interrupt requests may be frequently generated. take action (2) below. p.266 oscillation stabilization time on power application or after reset release the setting of this option is valid only when the crystal/ceramic oscillation clock is selected as the system clock source. no wait time elapses if the high-speed internal oscillation clock or external cl ock input is selected as the system clock source. p.270 control of reset pin because the option byte is referenced after reset release, if a low level is input to the reset pin before the option byte is referenced, then the reset state is not released. also, when setting 0 to rmce, connect the pull-up resistor. p.270 selection of system clock source because the x1 and x2 pins are also used as the p121 and p122 pins, the conditions under which the x1 and x2 pins can be used differ depending on the selected system clock source. (1) crystal/ceramic oscillation clock is selected the x1 and x2 pins cannot be used as i/o port pins because they are used as clock input pins. (2) external clock input is selected because the x1 pin is used as an ex ternal clock input pin, p121 cannot be used as an i/o port pin. (3) high-speed internal oscillation clock is selected p121 and p122 can be used as i/o port pins. p.270 if it is selected that low-speed internal oscillator cannot be stopped, the count clock to the watchdog timer (wdt) is fi xed to low-speed internal oscillation clock. p.271 chapter 18 hard option byte low-speed internal oscillates if it is selected that low-speed internal oscillator can be stopped by software, supply of the count clock to wdt is stopped in the halt/stop mode, regardless of the setting of bit 0 (lsrstop) of the low-speed internal oscillation mode register (lsrcm). si milarly, clock supply is also stopped when a clock other than the low-speed internal oscillation clock is selected as a count clock to wdt. while the low-speed internal oscillator is operating (lsrstop = 0), the clock can be supplied to the 8-bit timer h1 even in the stop mode. p.271 appendix d list of cautions user?s manual u17446ej5v0ud 406 (17/20) chapter classification function details of function cautions page chapter 18 hard option byte use of reset pin as an input- only port pin (p34) be aware of the following when re-era sing/-writing (by on -board programming using a dedicated flash memory progra mmer) an already-written device which has been set as ?the reset pin is used as an input-only port pin (p34)? by the option byte function. before supplying power to the target system, connect a dedicated flash memory programmer and turn its power on. if the power is supplied to the target system beforehand, the flash memory programming mode cannot be switched to. p.271 pg-fp5 gui software setting value example the above values are recommended values. depending on the usage environment these values may change, so set them after having performed sufficient evaluations. p.278 security settings after the security setting of the bat ch erase is set, erasure cannot be performed for the device. in addition, even if a write command is executed, data different from that which has already been written to the flash memory cannot be written because the erase command is disabled. p.281 self programming processing must be included in the program before performing self programming. p.282 no instructions can be executed while a self programming command is being executed. therefore, clear and restart the watchdog timer counter in advance so that the watchdog timer does not overflow during self programming. refer to table 19-10 for the time taken for the execution of self programming. p.285 interrupts that occur during self progr amming can be acknowledged after self programming mode ends. to avoid this oper ation, disable interrupt servicing (by setting mk0 and mk1 to ffh, and executing the di instruction) before a mode is shifted from the normal mode to the self programming mode with a specific sequence. p.285 ram is not used while a self programming command is being executed. p.285 if the supply voltage drops or the reset si gnal is input while the flash memory is being written or erased, writing/erasing is not guaranteed. p.285 the value of the blank data set du ring block erasure is ffh. p.285 set the cpu clock beforehand so that it is 1 mhz or higher during self programming. p.285 execute self programming after execut ing the nop and halt instructions immediately after executing a specific sequence to set self programming mode. at this time, the halt instruction is automatically released after 10 s (max.) + 2 cpu clocks (f cpu ). p.285 if the clock of the oscillator or an external clock is selected as the system clock, execute the nop and halt instru ctions immediately after executing a specific sequence to set self programming mode, wait for 8 s after releasing the halt status, and then execute self programming. p.285 check fprerr using a 1-bit memory manipulation instruction. p.285 chapter 19 soft flash memory self programming function the state of the pins in self programmi ng mode is the same as that in halt mode. p.285 appendix d list of cautions user?s manual u17446ej5v0ud 407 (18/20) chapter classification function details of function cautions page since the security function set via on- board/off-board programming is disabled in self programming mode, the self programming command can be executed regardless of the security function setting. to disable write or erase processing during self programming, set the protect byte. p.285 be sure to clear bits 5 to 7 of flash address pointer h (flaph) and flash address pointer h compare register (flaphc) to 0 before executing the self programming command. if the self programming command is executed with these bits set to 1, the device may malfunction. p.285 self programming function clear the value of the flcmd register to 00h immediately before setting to self programming mode and normal mode. p.285 cautions in the case of setting the self programming mode, refer to 19.8.2 cautions on self programming function. p.286 set the cpu clock beforehand so that it is 1 mhz or higher during self programming. p.286 execute self programming after execut ing the nop and halt instructions immediately after executing a specific sequence to set self programming mode. at this time, the halt instruction is automatically released after 10 s (max.) + 2 cpu clocks (f cpu ). p.286 if the clock of the oscillator or an external clock is selected as the system clock, execute the nop and halt instru ctions immediately after executing a specific sequence to set self programming mode, wait for 8 s after releasing the halt status, and then execute self programming. p.286 flpmc: flash programming mode control register clear the value of the flcmd register to 00h immediately before setting to self programming mode and normal mode. p.286 pfcmd: flash protect command register interrupt servicing cannot be executed in self programming mode. disable interrupt servicing (by executing the di instruction while mk0 and mk1 = ffh) between the points before executing the specific sequence that sets self programming mode and after executing the specific sequence that changes the mode to the normal mode. p.287 pfs: flash status register check fprerr using a 1-bit memory manipulation instruction. p.287 flaph and flapl: flash address pointers h and l be sure to clear bits 5 to 7 of flaph and flaphc to 0 before executing the self programming command. if the self programming command is executed with these bits set to 1, the device may malfunction. p.290 be sure to clear bits 5 to 7 of flaph and flaphc to 0 before executing the self programming command. if the self programming command is executed with these bits set to 1, the device may malfunction. p.290 set the number of the block subject to a block erase, verify, or blank check (same value as flaph) to flaphc. p.290 chapter 19 soft flash memory flaphc and flaplc: flash address pointer h compare register and flash address pointer l compare register clear flaplc to 00h when a block erase is performed, and ffh when a blank check is performed. p.290 appendix d list of cautions user?s manual u17446ej5v0ud 408 (19/20) chapter classification function details of function cautions page pp. shifting to self programming mode shifting to normal mode be sure to perform the series of o perations described above using the user program at an address where data is not erased or written. 293, 294, 296, 297 chapter 19 soft flash memory byte write operation if a write results in failure, erase the block once and write to it again. p.305 the 78k0s/kb1+ has an on-chip debug fu nction, which is provided for development and evaluation. do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. nec electronics is not liable for problem s occurring when the on-chip debug function is used. p.330 the constants described in the circui t connection example are reference values. if you perform flash prog ramming aiming at mass production, thoroughly evaluate whether the specifications of the target device are satisfied. p.330 chapter 20 hard on-chip debug function connecting qb- mini2 to 78k0s/kb1+ if debugging is performed with a real machine running, without using qb- mini2, write the user program using the qb-programmer. programs downloaded by the debugger include the monitor program, and such a program malfunctions if it is not controlled via qb-mini2. p.332 absolute maximum ratings product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. p.344 x1 oscillator when using the x1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring wi th the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. p.345 chapter 22 hard electrical specifica- tions (standard product, (a) grade product) a/d converter the conversion accuracy may be degraded if the analog input pin is used as an alternate i/o port or if a port is changed during a/d conversion. p.352 appendix d list of cautions user?s manual u17446ej5v0ud 409 (20/20) chapter classification function details of function cautions page absolute maximum ratings product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. p.356 x1 oscillator when using the x1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring wi th the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. p.358 chapter 23 hard electrical specifica- tions ((a2) grade product) a/d converter the conversion accuracy may be degraded if the analog input pin is used as an alternate i/o port or if a port is changed during a/d conversion. p.365 lead-free products products with ?a or ?ax at the end of the part number are lead-free products. p.373 for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. p.373 pp. do not use different soldering methods together (except for partial heating). 373, 374 chapter 25 hard recom- mended soldering conditions ? only the pins of the thd are heated when performing wave soldering. make sure that flow solder does not come in contact with the package. p.374 user?s manual u17446ej5v0ud 410 appendix e revision history e.1 major revisions in this edition page description throughout deletion of pd78f9232mc-5a4, 78f9234mc-5a4, 78f9232mc( a)-5a4, 78f9234mc(a)-5a4, 78f9232mc(a2)- 5a4, 78f9234mc(a2)-5a4 p. 6 modification of documents related to development software tools (user?s manuals) p. 18 modification of 1.4 78k0s/kx1+ product lineup pp. 38 to 41 modification of table 3-3 special function registers p. 274 19.4 writing with flash memory programmer ? deletion of flashpro4 and addition of qb-mini2 ? modification of remark p. 275 modification of and addition of remark to figure 19-2 environment for writing program to flash memory (flashpro5/qb-mini2) p. 276 modification of table 19-2 wiring between 78k0s/kb1+ and flashpro5/qb-mini2 p. 276 modification of and addition of remark to figure 19-3 wiring diagram with flashpro5/qb-mini2 (30-pin products) p. 280 modification of figure 19-7 communication commands pp. 299 to 301 19.8.6 example of block erase operation in self programming mode ? modification of desc ription and addition of note 2 ? modification of figure 19-20 example of block erase operation in self programming mode ? modification of an example of a program pp. 320 to 322 19.8.11 examples of operation when interrupt-disabled time should be minimized in self programming mode ? modification of figure 19-27 example of operation when interrupt-disabled time should be minimized (from erasure to blank check) ? modification of an example of a program p. 330 modification of caution in 20.1 connecting qb-mini2 to 78k0s/kb1+ p. 356 chapter 23 electrical specifications ((a2) grade product) ? target specifications specifications p. 375 modification of appendix a development tools appendix e revision history user?s manual u17446ej5v0ud 411 e.2 revision history up to previous editions the following table shows the revision history up to this ed ition. the ?applied to:? column indicates the chapters of each edition in which the revision was applied. (1/6) edition description applied to: addition of part number to 1.3 ordering information modification of operating temperature range in 1.5 78k0s/kx1+ product lineup chapter 1 overview addition of note to p34/reset, p121/x1 and p122/x2 in 2.1 pin function list addition of description to 2.2.3 p30 to p34 (port 3) addition of description to 2.2.7 reset chapter 2 pin functions addition of description to and modification of cautions in 4.2.3 port 3 chapter 4 port functions modification of description in (2) external event counter in 6.1 functions of 16-bit timer/event counter 00 modification of caution 2 in figure 6-2 format of 16-bit timer counter 00 (tm00) modification of caution 2 in figure 6-5 format of 16-bit timer mode control register 00 (tmc00) addition of caution to (1), (2), (3), and (4) in 6.4.3 pulse width measurement operations modification of figure 6-19 configuration diagram for pulse width measurement by free-running counter modification of figure 6-20 timing of pulse width measurement operation by free-running counter and one capture register (with both edges specified) and note modification of figure 6-22 timing of pulse width measurement operation with free-running counter (with both edges specified) and note modification of figure 6-24 timing of pulse width measurement operation by free-running counter and two capture registers (with rising edge specified) and note modification of <3> and <4> in (2) 16-bit timer counter 00 (tm00) operation of 6.5 cautions related to 16-bit timer/event counter 00 chapter 6 16-bit timer/event counter 00 modification of caution in (1) 8-bit compare register 80 (cr80) of 7.2 configuration of 8-bit timer 80 chapter 7 8-bit timer 80 modification of description in (2) 8-bit timer h compare register 11 (cmp11) of 8.2 configuration of 8-bit timer h1 modification of caution 1 in 8.4.2 operation as pwm output mode modification of (e) operation by changing cmp11 (cmp11 = 02h 03h, cmp01 = a5h) in figure 8-9 operation timing in pwm output mode chapter 8 8-bit timer h1 addition of description to caution 2 in figure 9-2 format of watchdog timer mode register (wdtm) chapter 9 watchdog timer modification of table 10-1 sampling time and a/d conversion time and note 1 modification of figure 10-3 format of a/d converter mode register (adm) and note 2 chapter 10 a/d converter addition of description to (7) input switch control register (isc) in 11.3 registers controlling serial interface uart6 2nd edition modification of value in table 11-4 set data of baud rate generator chapter 11 serial interface uart6 appendix e revision history user?s manual u17446ej5v0ud 412 (2/6) edition description applied to: modification of 13.4.2 multiple interrupt servicing addition of caution to example 1 in figure 13-10 example of multiple interrupts (1/2) addition of example 3 to figure 13-10 example of multiple interrupts (2/2) chapter 13 interrupt functions modification of reset signal in figure 14-3 halt mode release by reset signal generation modification of descri ption in and addition of note to (a) release by unmasked interrupt request in (2) of 14.2.2 stop mode modification of reset signal in figure 14-6 stop mode release by reset signal generation chapter 14 standby function modification of figure 15-1 block diagram of reset function chapter 15 reset function modification of figure 16-3 example of software processing after release of reset (1/2) chapter 16 power-on- clear circuit modification of figure 17-1 block diagram of low-voltage detector modification of intlvi and note 2 in figure 17-5 timing of low-voltage detector interrupt signal generation modification of (2) in appendix e revision history user?s manual u17446ej5v0ud 413 (3/6) edition description applied to: deletion of description on (t) product, (s) pro duct, (r) product, (t2) product throughout modification of 1.4 78k0s/kx1+ product lineup chapter 1 overview addition of caution 2 to 3.2.1 (3) stack pointer (sp) chapter 3 cpu architecture modification of figure 4-7 block diagram of p34 addition of caution to figure 4-17 format of port mode control register 2 chapter 4 port functions modification of caution 2 in 6.2 (1) 16-bit timer counter 00 (tm00) addition of 6.5 (23) external clock limitation chapter 6 16-bit timer/event counter 00 addition of caution to figure 10-8 format of port mode control register 2 (pmc2) addition of 10.6 (10) operating current at conversion waiting mode chapter 10 a/d converter addition of caution to 11.2 (1) receive buffer register 6 (rxb6) addition of caution 1 to and modification of caution 3 in 11.2 (3) transmit buffer register 6 (txb6) correction of note 3 in figure 11-5 format of asynchronous serial interface operation mode register 6 (asim6) (1/2) addition of notes 1 and 2 to and modification of cautions 1 , 2 and 3 in figure 11-5 format of asynchronous serial interface operation mode register 6 (asim6) (2/2) modification of caution in 11.3 (6) asynchronous serial interface control register 6 (asicl6) modification of caution 1 in figure 11-10 format of asynchronous serial interface control register 6 (asicl6) modification of caution in 11.4.2 (1) registers used partial modification of description in 11.4.2 (2) (c) normal transmission partial modification of de scription in and addition of caution 1 to 11.4.2 (2) (d) continuous transmission chapter 11 serial interface uart6 addition of caution 2 to 17.3 (2) low-voltage detection level select register (lvis) chapter 17 low- voltage detector addition of 18.3 caution when the reset pin is used as an input-only port pin (p34) chapter 18 option byte addition of description to 19.6.1 x1 and x2 pins addition of remark 1 to 19.8 flash memory programming by self writing modification of description of internal verify 1 in and addition of description and remark of internal verify 2 to table 19-11 self programming controlling commands partial modification of and addition to 19.8.2 cautions on self programming function addition of cautions 2 , 3 and 5 to and modification of caution 4 in figure 19-12 format of flash programming mode control register (flpmc) modification of caution in and addition of description on fprerr to 19.8.3 (2) flash protect command register (pfcmd) 3rd edition addition of caution to 19.8.3 (3) flash status register (pfs) chapter 19 flash memory appendix e revision history user?s manual u17446ej5v0ud 414 (4/6) edition description applied to: modification of description and note of internal verify 1 in and addition of description of internal verify 2 to figure 19-15 format of flash programming command register (flcmd) modification of caution in figure 19-16 format of flash address pointer h/l (flaph/flapl) and caution 1 in format of flash address pointer h/l compare registers (flaphc/flaplc) addition of description to 19.8.4 example of shifting normal mode to self programming mode and 19.8.5 example of shifting self programming mode to normal mode addition of description of internal verify 1 and 2 to 19.8.9 examples of internal verify operation in self programming mode addition of description to 19.8.10 examples of operation when command execution time should be minimized in self programming mode and 19.8.11 examples of operation when interrupt-disabled time should be minimized in self programming mode chapter 19 flash memory ? correction of max. value of low-level input voltage (v il3 ) ? correction of conditions of high-level output voltage (v oh2 ) ? modification of max. values of high-le vel input leakage current, low-level input leakage current, high-level output leak age current and low-level output leakage current ? modification of max. va lues of supply current (i dd5 ) in stop mode ? addition of setting range of cpu cl ock and peripheral clock frequency to ac characteristics ? modification of caution in a/d converter characteristics chapter 21 electrical specifications (standard product, (a) grade product) ? correction of max. value of low-level input voltage (v il3 ) ? correction of conditions of high-level output voltage (v oh2 ) ? addition of formula to calculate power c onsumption of internal pull-up resistor ? addition of setting range of cpu cl ock and peripheral clock frequency to ac characteristics ? modification of caution in a/d converter characteristics chapter 22 electrical specifications (target values) ((a2) grade product) deletion of chapter 25 package marking information chapter 25 package marking information modification of a.4 flash memory writing tools 3rd edition addition of a.5.1 when using in-circuit emulator qb-78k0skx1 (under development) and a.5.2 when using in-circuit emulator qb-mini2 appendix a development tools appendix e revision history user?s manual u17446ej5v0ud 415 (5/6) edition description applied to: ? addition of sdip package products ( pd78f9232cs-caa-a, 78f9234cs-caa-a) ? addition of products ( pd78f9232mc(a)-cab-ax, 78f9234mc(a)-cab-ax, 78f9232mc(a2)-cab-ax, 78f9234mc( a2)-cab-ax) to ssop package throughout modification of 1.1 features modification of 1.2 ordering information 1.3 pin configuration (top view) ? modification of description of av ref modification of 1.4 78k0s/kx1+ product lineup modification of 1.6 functional outline chapter 1 overview 2.1 pin function list , 2.2.9 av ref ? modification of description of av ref function chapter 2 pin functions ? addition of note 4 to table 10-1 sampling time and a/d conversion time ? addition of note 5 to figure 10-3 format of a/d converter mode register (adm) chapter 10 a/d converter modification of caution 3 chapter 15 reset function 19.4 writing with flash memory programmer ? modification of the dedicated flash memo ry programmer (addition of flashpro5 and deletion of pg-fpl2) ? modification of remark 19.5 programming environment ? addition of flashpro5 and qb-mini2 to the dedicated flash memory programmer ? addition of description about conn ection to flashpro5/qb-mini2 ? deletion of pg-fpl2 from the dedicated flash memory programmer modification of figure 19-5 pg-fp5 gui software setting example figure 19-7 communication commands ? addition of flashpro5 and qb-mini2 to the dedicated flash memory programmer ? deletion of pg-fpl2 from the dedicated flash memory programmer addition of note to table 19-10 self programming controlling commands chapter 19 flash memory addition of this chapter chapter 20 on-chip debug function ? modification of x1 oscillator characteristics ? addition of setting range of cpu cl ock and peripheral clock frequency to ac characteristics chapter 22 electrical specifications (standard product, (a) grade product) ? modification of x1 oscillator characteristics ? addition of setting range of cpu cl ock and peripheral clock frequency to ac characteristics chapter 23 electrical specifications (target values) ((a2) grade product) addition of package drawings of additional products chapter 24 package drawing 4th edition addition of recommended soldering conditions of additional products chapter 25 recommended soldering conditions appendix e revision history user?s manual u17446ej5v0ud 416 (6/6) edition description applied to: modification of figure a-1 development tools a.4 flash memory writing tools ? addition of flashpro5 and qb-mini2 ? deletion of pg-fpl2 modification of a.5.1 when using in-circuit emulator qb-78k0skx1 deletion of a.5.3 when using in-circuit emulator ie-78k0s-ns or ie-78k0s-ns-a and a.5.4 when using in-circuit emulator qb-78k0skx1mini modification of a.6 debugging tools (software) appendix a development tools 4th edition modification of this chapter appendix b notes on designing target system published by: nec electronics corporation (http://www.necel.com/) contact: http://www.necel.com/support/ |
Price & Availability of UPD78F9234MCA-5A4-A
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |